
Preliminary W29S201
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to operate at a system clock frequency as high as 50/40Mhz with only 3 initial wait-states (3-1-1-1)
required for the initial random access depending on the host performance and capability on the starting &
ending burst address. Refer to the timing waveforms for further details.
Reset Operation
The RESET input pin can be used in some application. When RESET pin is at high state, the device
is in normal operation mode. When RESET pin is driven low for at least a period of TRP, it will halts the
device and all outputs are at high impedance state. The device also resets the internal state machine to
reading array data. The operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to assure data integrity.
As the high state re-asserted to the
RESET pin, the device will return to read or standby mode, it depends on the control signals.
The
system can read data TRH after the RESET pin returns to VIH. The other function for RESET pin is
temporary reset the boot block.
By applying the 12V to RESET pin, the boot block can be
reprogrammed even though the boot block lockout function is enabled.
Boot Block Operation
There is one 8K-word boot block in this device, which can be used to store boot code. It is located in the
first 8K words of the memory with the address range from 0000(hex) to 1FFF(hex).
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout); other memory
locations can be changed by the regular programming method. Once the boot block programming
lockout feature is activated, the chip erase function will be disable.
There is one condition that the lockout feature can be overrides. Just apply 12V to RESET pin, the
lockout feature will temporary be inactivated and the block can be erased/programmed. Once the
RESET pin returns to TTL level, the lockout feature will be activated again.
In order to detect whether the boot block feature is set on the 8K-words block, users can perform
software command sequence: enter the product identification mode (see Command Codes for
Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If
the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the output data
in DQ0 is "0", the lockout feature is inactivated and the block can be erased or programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-word
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. The entire memory array will be erased to FF(hex). by the chip erase operation if
the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function will be disable. The device will automatically return to normal read
mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of
erase cycle.