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參數(shù)資料
| 型號： | W29S201T-55 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 128K X 16 FLASH 5V PROM, 17 ns, PDSO48 |
| 封裝： | 12 X 20 MM, TSOP1-48 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大小： | 253K |
| 代理商： | W29S201T-55 |
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Preliminary W29S201
Publication Release Date: April 1999
- 3 -
Revision A1
FUNCTIONAL DESCRIPTION
Synchronous Burst & Asynchronous Read Mode Features
The Winbond’s W29S201 Flash device requires 3 additional control pins for synchronous burst read
operations: Synchronous/Assynchronous Read Mode Select ( MODE ), Address Valid ( ADV ), and
Clock (CLK). This synchronous read mode feature allows W29S201 to be interfaced easily to a wide
range of DSP, microprocessors, micro-controllers for higher performance read operations. All these 3
pins are only activated internally when chip is selected (CE =VIL). The MODE input pin is used to select
either synchronous or assynchronous read mode for the memory read operations. If MODE is held low,
the synchronous burst read mode is selected for the read operation, and if MODE is held high then
assynchronous read mode is selected for all read operations (the ADV and CLK are ignored by the
Flash internally). The ADV input pin is used when the chip is selected in the synchronous read mode
(CE =VIL and MODE =VIL) to load the initial random address into the Flash at the rising edge of the clock
when ADV =VIL, and to increment the internal address counter at the rising edge of the clock when
ADV =VIH. The CLK input pin can be tied to the system clock to provide the fundamental timing and
array synchronous burst read operating frequency. Both ADV and CLK inputs are only enabled when
chip is selected to operate in the synchronous burst read mode (CE =VIL and MODE =VIL). The MODE
input pin is internally pulled high for applications which does not require the synchronous burst read
operations, hence allowing these additional 3 pins to be considered as the No Connect (NC) pins.
However, Winbond recommends that these 3 pins be driven at known logic level externally if possible.
The states of these 3 additional pins are ignored during all write operations.
Assynchronous Random Read Mode
The assynchronous read operation of the W29S201 is controlled by CE and OE, both of which have to
be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high,
the chip is de-selected and only standby power will be consumed. OE is the output control and is used
to gate data from the output pins. The data bus is in high impedance state when either CE or OE is
high. Refer to the timing waveforms for further details.
Synchronous Burst Read Mode
Beside being assynchronously controlled by CE and OE pins similarly as in the assynchronous read
operations, the selected W29S201 Flash device when used in synchronous burst read operation mode
( MODE =VIL) requires the host to provide the initial random burst address by driving the ADV pin low at
the rising edge of the clock (CLK) to latch the initial burst random address into the Flash device. Initial
output data (at DQ pins) become available 2 clock cycles (or 3 clock cycles depending on starting
address, refer to the timing waveforms for further details). By driving the ADV pin high at the rising edge
of the clock enables the W29S201 device to read data from the next binary incremental address (linear
burst mode). Sequential output data becomes available TKQV (15/17) ns of burst access time after the
rising edge of the clock (always 2 CLK periods after the address increment started, i.e., ADV pin went
high). There is no burst length limitation for the W29S201 device architecture, hence allowing the host to
sequentially read out the entire memory data (128K words) with just one burst read operation. The
W29S201 also supports full memory array linear wrap-around mode. The W29S201Q-45/55 can be used
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