參數(shù)資料
型號(hào): W25Q32BWZPIP
廠商: WINBOND ELECTRONICS CORP
元件分類: PROM
英文描述: 4M X 8 SPI BUS SERIAL EEPROM, DSO8
封裝: 6 X 5 MM, GREEN, WSON-8
文件頁數(shù): 24/72頁
文件大小: 2212K
代理商: W25Q32BWZPIP
W25Q32BW
- 30 -
10.2.14 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit
(QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. To ensure optimum
performance the High Performance Mode (HPM) instruction (A3h) must be executed once, prior to the
Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 13a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bit M4 = 0, then the next Fast Read Quad I/O instruction (after /CS is
raised and then lowered) does not require the EBh instruction code, as shown in figure 13b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after
/CS is asserted low. If the “Continuous Read Mode” bit M4 = 1, the next instruction (after /CS is raised
and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (See 10.2.19 for detail descriptions).
Byte 1
Byte 2
Byte 1
Byte 2
Figure 13a. Fast Read Quad I/O Instruction Sequence Diagram (Initial Fast Read Quad I/O instruction or previous M4 = 1)
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