參數(shù)資料
型號(hào)： W167B
廠商： Cypress Semiconductor Corp.
英文描述： 133-MHz Spread Spectrum FTG for Pentium II Platforms
中文描述： 133 - MHz的擴(kuò)頻FTG的奔騰II平臺(tái)
文件頁(yè)數(shù)： 1/18頁(yè)
文件大?。?/td> 180K
代理商： W167B
PRELIMINARY
133-MHz Spread Spectrum FTG for Pentium II Platforms
W167B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
November 2, 1999
408-943-2600
Features
Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
Three copies of CPU outputs selectable frequency
Three copies of 3V66 selectable frequency output at
3.3V
Ten copies of PCI clocks (selectable frequency), 3.3V
One double strength 14.318-MHz reference output at
3.3V
One copy of 48-MHz USB clock
One copy of selectable 24-/48-MHz for SIO
One copy of CPU-divide-by-2 output as reference input
to Direct Rambus Clock Generator (Cypress W134)
Three copies of IOAPIC
Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... V
DDQ2
= 2.5V±5%
V
DDQ3
= 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew:...................................... 175 ps
IOAPIC, 3V66 Output Skew:....................................... 250 ps
PCI0:8 Pin to Pin Skew:.............................................. 500 ps
Duty Cycle:................................................................ 45/55%
Spread Spectrum Modulation:................................... ±0.25%
CPU to 3V66 Output Offset:............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.
Table 1. Pin Selectable Frequency
SEL133/
100#
SEL2 SEL1 SEL0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
CPU
MHz
133.3
138
143
148
150
152.5
155
160
100.2
105
114
120
66.8
124
128.5
133.9
3V66
MHz
66.7
69
71.5
74
75
76.3
77.5
80
66.8
70
76
80
66.8
82.7
64.3
67
PCI
MHz
33.3
34.5
35.8
37
37.5
38.1
38.8
40
33.4
35
38
40
33.4
41.3
32.1
33.5
IOAPIC
MHz
16.7
17.3
17.9
18.5
18.8
19.1
19.4
20
16.7
17.5
19
20
16.7
20.7
16.1
16.7
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Block Diagram
Pin Configuration
Note:
1.
Internal 250-k
pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
[1]
REF2X
CPU_[0:2]
CPUdiv2
3V66_[0:2]
XTAL
OSC
PLL 1
X2
X1
PCI_[2:9]
IOAPIC[0:2]
48MHz/SEL0*
PLL2
÷2
Power
Down
Logic
÷2/÷1.5
÷2
÷2
3
3
PWRDWN#
3
÷2
SIO/24_48#MHz
Serial
Logic
SEL133/100#
SCLK
SDATA
PCI0/SEL2*
PCI1/SEL1*
8
IOAPIC2
REF2X
VDDQ3
X1
X2
GND
SEL2*/PCI0
SEL1*/PCI1
VDDQ3
PCI2
PCI3
PCI4
PCI5
GND
PCI6
PCI7
VDDQ3
PCI8
PCI9
GND
3V66_0
3V66_1
3V66_2
VDDQ3
W
GND
VDDQ2
IOAPIC0
IOAPIC1
GND
VDDQ2
CPUdiv2
GND
VDDQ2
CPU2
GND
VDDQ2
CPU1
CPU0
SDATA
VDDQ3
GND
PWRDN#*
SCLK
VDDQ3
SIO/24_48#MHz
*
48MHz/SEL0*
GND
SEL133/100#
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q#
VDDQ2
VDDQ3
VDDQ2
VDDQ3
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