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參數(shù)資料
| 型號(hào)： | W158HT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK98 SSCG CK98 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:24 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 133MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
W158
..... Document #: 38-07164 Rev. *A Page Page 8 of 12 of 12
3.3V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[35]
Notes:
32. X1 input threshold voltage (typical) is VDD/2.
33. The W158 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
34. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
35. Period, jitter, offset, and skew measured on rising edge at 1.5V.
36. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
Crystal Oscillator
VTH
X1 Input threshold Voltage[32]
1.65
V
CLOAD
Load Capacitance, Imposed on
External Crystal[33]
18
pF
CIN,X1
X1 Input Capacitance[34]
Pin X2 unconnected
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
5
pF
COUT
Output Pin Capacitance
6
pF
LIN
Input Pin Inductance
7nH
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency
Note 36
66.6
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior
to frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
15
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