參數(shù)資料
型號(hào)： W144
廠商： IC WORKS INC
元件分類(lèi)： XO, clock
英文描述： 440BX AGPset Spread Spectrum Frequency Synthesizer(440BX AGP裝置寬頻譜譜頻率合成器)
中文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
文件頁(yè)數(shù)： 1/14頁(yè)
文件大小： 155K
代理商： W144
PRELIMINARY
440BX AGPset Spread Spectrum
Frequency Synthesizer
W144
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 2, 1999, rev. **
Features
Maximized EMI suppression using Cypress’s Spread
Spectrum technology
Single chip system frequency synthesizer for Intel
440BX AGPset
Two copies of CPU output
Six copies of PCI output
One 48-MHz output for USB
One 24-MHz output for SIO
Two buffered reference outputs
One IOAPIC output
Thirteen SDRAM outputs provide support for 3 DIMMs
Supports frequencies up to 150 MHz
I
2
C interface for programming
Power management control inputs
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
V
DDQ3
: .................................................................... 3.3V±5%
V
DDQ2
: .................................................................... 2.5V±5%
SDRAMIN to SDRAM0:11 Delay: ..........................3.7 ns typ.
SDRAM0:11 (leads) to SDRAM_F Skew:..............0.4 ns typ.
Table 1. Mode Input Table
Mode
Pin2
0
1
PCI_STOP#
REF0
Table 2. Pin Selectable Frequency
Input Address
FS2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
CPU_F, CPU1
(MHz)
133.3
124
150
140
105
110
115
120
100
133.3
112
103
66.8
83.3
75
124
PCI_F, 1:5 (MHz)
33.3 (CPU/4)
31 (CPU/4)
37.5 (CPU/4)
35 (CPU/4)
35 (CPU/3)
36.7 (CPU/3)
38.3 (CPU/3)
40 (CPU/3)
33.3 (CPU/3)
44.43 (CPU/3)
37.3 (CPU/3)
34.3 (CPU/3)
33.4 (CPU/2)
41.7 (CPU/2)
37.5 (CPU/2)
41.3 (CPU/3)
FS3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
FS1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Intel is a registered trademark of Intel Corporation. I
2
C is a trademark of Philips Corporation.
Logic Block Diagram
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
CPU1
PCI_F/MODE
PCI1/FS3
OSC
PLL Ref Freq
Stop
PLL 1
X2
X1
VDDQ3
CStop
Stop
PCI2
PCI3
PCI4
PCI5
48MHz/FS0
VDDQ3
PLL2
÷2,3,4
VDDQ2
CLK_STOP#
VDDQ3
IOAPIC
I
2
C
Logic
SDATA
SCLK
I/O Pin
Control
SDRAM0:11
SDRAMIN
12
CStop
CPU_F
÷2
SDRAM_F
Pin Configuration
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1/FS3
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
I
2
C
{
GND
SDATA
SCLK
W
VDDQ2
IOAPIC
REF1/FS2*
GND
CPU_F
CPU1
VDDQ2
CLK_STOP#
SDRAM_F
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
VDDQ3
48MHz/FS0*
24MHz/FS1*
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note:
1.
Internal pull-up resistors should not be relied upon for setting
I/O pins HGH. Pin function with parentheses determined by
MODE pin resistor strapping. Unlike other I/O pins, input FS3
has an internal pull down resistor.
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