參數(shù)資料
型號(hào)： VV5404C001
廠商： 意法半導(dǎo)體
英文描述： Mono and Colour Digital Video CMOS Image Sensors
中文描述： 莫諾和數(shù)字視頻彩色CMOS圖像傳感器
文件頁(yè)數(shù)： 42/54頁(yè)
文件大?。?/td> 786K
代理商： VV5404C001
VV5404 & VV6404
CD5404-6404F-A
42/54
6.
VV5404 and VV6404 generate a system clock when a quartz crystal or ceramic resonator circuit is connected to the
CLKI and CLKO pins. The device can also be driven directly from an external clock source driving CLK.
If CLKI is generated for the video sensor by the receiving device it must be active during serial interface
communications for at least 16 clock cycles before the serial communications start bit and for at least 16 cycles after
the serial communications stop bit.
The synchronisation input, SIN, synchronises the clock divider logic in addition to the main clock generation and the
video timing control block.
.
Clock Signal
For greater flexibility the input frequency can be divided by 2, 4, 8 or 16 to select the pixel clock frequency. The clock
divisor serial register selects the input clock frequency divisor.
The clock signal must be a square wave with a 50% (+/- 10%) mark:space ratio. Table 28 specifies the maximum and
minimum pixel clock frequencies for the module. Table 29 and Table 29 specify the relationship between the input
clock, CLKI, and the pixel clock frequency for the different settings of the sensor’s internal clock divider.
This translates into a maximum input clock frequency of 7.15909 MHz if a clock divisor of 2 is used (the default - Table
29). Thus if a 14.31818 MHz crystal is used, only the 4, 8 and 16 clock divisors should be used (Table 29).
MHz
Minimum Pixel Rate
0.44744
Maximum Pixel Rate
3.57954
Table 28 : Maximum and Minimum Pixel Rates
X1
C2
C1
R1
32
31
VV5/6404
CMOS
Driver
Clock
Source
R2
C1 = C2 = 47 pF
X1 = 14.31818 MHz
R1 = 1 M
R2 = 510
CLK
CLOCK
DIVISION
CLKI
CLKO
32
31
VV5/6404
CLK
CLOCK
DIVISION
CLKI
CLKO
Figure 27 : Camera Clock Sources
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VV5430C001 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Monochrome Analog Output CMOS Image Sensors
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