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參數(shù)資料
| 型號： | VSC9142 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH 2.5Gbps Transport Terminating Transceiver |
| 中文描述： | MUX/DEMUX, PBGA320 |
| 封裝： | TBGA-320 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 259K |
| 代理商： | VSC9142 |
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G56054-0, Rev 1.0
SONET/SDH 2.5Gbps Transport Terminating Transceiver
VSC9142
.
4.0 Electrical & Mechanical Data
Page 23
.
Table 1.1
Hardware Signal Definitions (5 of 12)
Pin Label
POS Mode:
TPRTY
ATMMode:
TUPRTY
Pad
C8
I/O
I
Type
TTL
Signal Name
Transmt Bus
Parity
Description
POS Mode:
TRPRTY is the odd/even (programmable, default
odd) parity bit over TDAT[31..0]. The signal is only valid when
asserted simultaneously with TENB.
ATMMode:
TUPRTY is the odd/even (programmable, default
odd) parity bit over TUDATA[31..0], driven by the ATM layer.
The signal is valid when asserted simultaneously with TUENB*
POS Mode:
TMOD[1]
TMOD[0]
A7
B7
I
TTL
Transmt Word
Modulo
POS Mode only:
These inputs are used to qualify TDAT
x
data
octets. The state of TMOD[1,0] defines which of the four TDAT
octets contain valid data when both TEOP and TENB are
asserted. Non-EOP words always contain four valid TDAT
octets.
POS Mode:
TSOP is asserted (active high) by the Packet layer
to indicate that TDAT
x
contains the first valid octet of a new
packet. The signal is valid when asserted simultaneously with
TENB. The packet interface can be operated without using this
signal.
ATMMode:
TUSOC is asserted (active high) by the ATM layer
to indicate that TUDATA
x
contains the first valid octet of the
cell. The signal is only valid when asserted simultaneously with
TUENB*
POS Mode only:
TEOP is asserted (active high) by the Packet
layer to indicate that TDAT
x
contains the last valid octet of the
packet. Only valid when asserted simultaneously with TENB.
POS Mode:
DTPA transitions high when a programmable
mnimumnumber of octets are available in the Tx FIFO. Once
high, the DTPA indicates that the Tx FIFO is not full. When
DTPA transitions low, it optionally indicates that the Tx FIFO is
full or near full.
ATMMode:
TUFULL*/TUCLAV is indicates “Full” or “Cell
Available” status of UTOPIA transmt interface for flow control.
TUFULL*is for word-level flow control; TUCLAV is for cell-level
flow control. Polarity is selectable via an internal register bit (i.e.,
TUFULL*active low/TUCLAV active high, or vice versa).
POS Mode only:
An active TERR flag can be used to force
HDLC frame abortion, or insertion of FCS error in the
transmtted HDLC/PPP frames. The TERR value is only valid for
TEOP-marked words, and is ignored for all other word writes.
POS Mode:
TENB is used by the Packet layer to indicate
cycles when TDAT
x
contains valid packet data (active low).
ATMMode:
TUENB*is used by the ATMlayer to indicate
cycles when TUDATA
x
contains valid cell data (active low).
POS Mode:
TFCLK is a reference clock provided by the Packet
layer to the PHY layer to synchronize transfers on TDAT
x
.
ATMMode:
TUCLK is a reference clock provided by the ATM
layer to the PHY layer to synchronize transfers on TUDATA
x
.
POS Mode:
TFCLKO is the TFCLK transfer synchronization
reference clock fromthe Packet layer looped out.
ATMMode:
TUCLKO is the TUCLK transfer synchronization
reference clock fromthe ATM layer looped out.
POS Mode:
TSOP
ATMMode:
TUSOC
C9
I
TTL
Transmt Start of
Packet
or
UTOPIA
Transmt Start of
Cell
POS Mode:
TEOP
D10
I
TTL
Transmt End of
Packet
POS Mode:
DTPA
ATMMode:
TUFULL*/
TUCLAV
A9
O
TTL
Transmt Polled-
PHY Packet
Available
or
Transmt Full/Cell
Available
POS Mode:
TERR
B9
I
TTL
Transmt Error
Indicator
POS Mode:
TENB
ATMMode:
TUENB*
POS Mode:
TFCLK
ATMMode:
TUCLK
POS Mode:
TFCLKO
ATMMode:
TUCLKO
C10
I
TTL
Transmt Write
Enable
A10
I
TTL
Transmt Write
Clock
D
B10
O
TTL
Transmt Write
Clock Looped
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