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參數(shù)資料
| 型號： | VSC838UG |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | RECTIFIER BRIDGE 25A 200V 300A-ifsm 1.1V-vf 5uA-ir GBPC 100/TRAY |
| 中文描述： | 36-BIT, DSP-CROSSBAR SWITCH, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, TBGA-480 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 296K |
| 代理商： | VSC838UG |
VITESSE
Preliminary Data Sheet
VSC838
3.2Gb/s
36x37 Crosspoint Switch
G52351-0, Rev 3.0
02/12/01
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
AC Characteristics
Table 1: Data Path
NOTES:
(1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 2
23
-1 PRBS data pattern.
Table 2: Program Interface Timing
Parameter
Description
Min
Typ
Max
Units
f
RATE
T
SKW
T
PDAY
t
R
, t
F
t
R
, t
F
t
jR
t
jP
Maximum data rate
Channel-to-channel delay skew
Propagation Delay from an A input to a Y output
High-speed input rise/fall times, 20% to 80%
High-speed output rise/fall times, 20% to 80%
Output added delay jitter, rms
(1, 2)
Output added delay jitter, peak-to-peak
(1, 2)
-
-
-
-
-
-
-
-
3.2
-
-
150
150
10
40
Gb/s
ps
ps
ps
ps
ps
ps
300
750
-
-
Parameter
Description
Min
Typ
Max
Units
T
sWR
Setup time from INCHAN[5:0] or OUTCHAN5:0] to rising edge of
WR.
Hold time from rising edge of WRB to INCHAN[5:0] or
OUTCHAN[5:0].
Pulse width (HIGH or LOW) on LOAD
Setup time from CS to falling edge of LOAD or ALE_SCN in parallel or
burst mode, or rising edge of LOAD in serial mode.
Hold time of CS rising edge after LOAD or ALE_SCN rising in parallel
or burst mode, or falling edge of LOAD in serial mode, or falling edge of
CONFIG in any mode.
Pulse width (HIGH or LOW) on CONFIG.
Setup time from INCHAN0(SDIN) to INCHAN1(SCLK) rising.
Hold time of INCHAN0(SDIN) after INCHAN1(SCLK) rising.
Minimum period of SCLK in serial mode.
Setup time from LOAD to INCHAN1(SCLK) rising.
Hold time of LOAD after INCHAN1(SCLK) rising.
Setup time from SERIAL rising to INCHAN1(SCLK) rising when
entering serial mode or SERIAL falling to LOAD falling when entering
parallel mode or SERIAL falling to LOAD rising when entering burst
mode.
Hold time from INCHAN1(SCLK) rising to SERIAL falling when
exiting serial mode.
Delay from INCHAN1(SCLK) rising to SDOUT, 20pF load.
Pulse width (HIGH or LOW) on INIT.
Setup time from ALE_SCN to INCHAN1(SCLK) rising when starting
or completing a serial read-back sequence.
Hold time of ALE_SCN after INCHAN1(SCLK) rising when starting or
completing a serial read-back sequence.
3.35
—
—
ns
T
hWR
1.45
—
—
ns
T
PWLW
6.75
—
—
ns
T
sCS
0
—
—
ns
T
hCSB
0
—
—
ns
T
PWCFG
T
sSDIN
T
hSDIN
T
perSCLK
T
sLOAD
T
hLOAD
6.75
1.65
1.0
15
1.85
0.95
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
T
sSERIAL
0.90
—
—
ns
T
hSERIAL
0
—
—
ns
T
dSDOUT
T
PWINIT
—
6.75
—
—
6.20
—
ns
ns
T
sSCAN
1.65
—
—
ns
T
hSCAN
1.0
—
—
ns
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