參數(shù)資料
型號: VSC837UG
廠商: VITESSE SEMICONDUCTOR CORP
元件分類: 數(shù)字信號處理外設
英文描述: DIODE ZENER SINGLE 150mW 3Vz 5mA-Izt 0.0667 10uA-Ir 1 SOT-523 3K/REEL
中文描述: 68-BIT, DSP-CROSSBAR SWITCH, PBGA480
封裝: 37.50 MM, TBGA-480
文件頁數(shù): 5/26頁
文件大小: 340K
代理商: VSC837UG
VITESSE
Preliminary Data Sheet
VSC837
3.2Gb/s
68x68 Crosspoint Switch
G52309-0, Rev 3.0
02/16/01
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
AC Characteristics
Table 1: Data Path
NOTES:(1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 2
23
-1 PRBS data pattern.
Table 2: Program Interface Timing
Symbol
Parameter
Min
Typ
Max
Units
f
RATE
t
SKW
t
PDAY
t
R
, t
F
t
R
, t
F
t
JR
t
JP
Maximum Data Rate
Channel-to-channel delay skew
Propagation Delay from an A input to a Y output
High-speed input rise/fall times, 20% to 80%
High-speed output rise/fall times, 20% to 80%
Output added delay jitter, rms
(1, 2)
Output added delay jitter, peak-to-peak
(1, 2)
300
750
3.2
150
150
10
40
Gb/s
ps
ps
ps
ps
ps
ps
Symbol
Parameter
Min
Typ
Max
Units
t
sWRB
t
hWRB
t
pwLW
Setup time from INCHAN[6:0] or OUTCHAN[6:0] to rising edge of WRB
Hold time from rising edge of WRB to INCHAN[6:0] or OUTCHAN[6:0]
Pulse width (HIGH or LOW) on LOAD
Setup time from CSB to falling edge of LOAD or ALE_SCN in parallel or burst
mode, or rising edge of LOAD in serial mode.
Hold time of CSB rising edge after LOAD or ALE_SCN rising in parallel or
burst mode, or falling edge of LOAD in serial mode, or falling edge of CONFIG
in any mode.
Pulse width (HIGH or LOW) on CONFIG
Setup time from INCHAN0_SDIN to INCHAN1_SCLK rising
Hold time of INCHAN0_SDIN after INCHAN1_SCLK rising
Minimum period of SCLK in serial mode
Setup time from LOAD to INCHAN1_SCLK rising
Hold time of LOAD after INCHAN1_SCLK rising
Setup time from SERIAL rising to INCHAN1_SCLK rising when entering serial
mode or SERIAL falling to LOAD falling when entering parallel mode or
SERIAL falling to LOAD rising when entering burst mode.
Hold time from INCHAN1_SCLK rising to SERIAL falling when exiting serial
mode.
Setup time from BURST rising to LOAD rising when entering burst mode or
BURST falling to LOAD falling when entering parallel mode.
Hold time from LOAD rising to BURST falling when exiting burst mode.
Delay from INCHAN1_SCLK rising to SDOUT, 20pF load.
Pulse width (HIGH or LOW) on INITB
Setup time from ALE_SCN to INCHAN1_SCLK rising when starting or
completing a serial read-back sequence.
Hold time of ALE_SCN after INCHAN1_SCLK rising when starting or
completing a serial read-back sequence.
3.35
1.45
6.75
ns
ns
ns
t
sCSB
0
ns
t
hCSB
0
ns
t
pwCFG
t
sSDIN
t
hSDIN
t
perSCLK
t
sLOAD
t
hLOAD
6.75
1.65
1.0
15
1.85
0.95
ns
ns
ns
ns
ns
ns
t
sSERIAL
0.90
ns
t
hSERIAL
0
ns
t
sBURST
1.85
ns
t
hBURST
t
dsDOUT
t
pwINITB
2.45
6.75
6.20
ns
ns
ns
t
sSCAN
1.65
ns
t
hSCAN
1.0
ns
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