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參數(shù)資料
| 型號： | VSC830 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch |
| 中文描述： | 2.7Gb / s的異步雙2x2交叉點開關 |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 195K |
| 代理商： | VSC830 |
VITESSE
Data Sheet
VSC830
Dual 2x2 Crosspoint Switch
2.7Gb/s Asynchronous
Page 8
G52192-0, Rev 4.0
05/23/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Table 10: Pin Identification
Signal Name
Pin(s)
Function
Description
V
CC
1, 5, 7, 11, 12,
16, 28, 40, 44
34, 35
32, 33
23, 24
21, 22
38
29
27
18
Positive Supply
Global supply for chip
V
EE
1A
V
EE
2A
V
EE
1B
V
EE
2B
V
CC
P1A
V
CC
P2A
V
CC
P1B
V
CC
P2B
Negative Supply
Negative Supply
Negative Supply
Negative Supply
Positive Supply
Positive Supply
Positive Supply
Positive Supply
For channel output 1A. Must always be powered on.
For output 2A. Connect to VCC to power-off.
For output 1B. Connect to VCC to power-off.
For output 2B. Connect to VCC to power-off.
Output driver supply for channel 1A
Output driver supply for channel 2A
Output driver supply for channel 1B
Output driver supply for channel 2B
Input termination enable for the
“
A
”
switch.
Normally low (VEE). Connect to VCC to enable
internal 100 ohm termination between AxA+ inputs.
Input termination enable for the
“
B
”
switch.
Normally low (VEE). Connect to VCC to enable
internal 100
termination between AxA+ inputs.
PECL/TTL interface control
Channel 1A differential signal input
Channel 1A input selector
Channel 1A differential output
Channel 2A differential signal input
Channel 2A input selector
Channel 2A differential output
Channel 1B differential signal input
Channel 1B input selector
Channel 1B differential output
Channel 2B differential signal input
Channel 2B input selector
Channel 2B differential output
TERM_ENABLE_A
39
Termination Enable
TERM_ENABLE_B
17
Termination Enable
PEMODE
A1A±
S1A
Y1A±
A2A±
S2A
Y2A±
A1B±
S1B
Y1B±
A2B±
S2B
Y2B±
6
Control
PECL Input
PECL/TTL Input
PECL Output
PECL Input
PECL/TTL Input
PECL Output
PECL Input
PECL/TTL Input
PECL Output
PECL Input
PECL/TTL Input
PECL Output
41, 42
43
37, 36
3, 4
2
31, 30
8, 9
10
26, 25
14, 15
13
20, 19
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