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參數(shù)資料
| 型號： | VSC7105QF |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PQFP44 |
| 封裝： | 14 X 14 MM, HEAT SPREADER, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 185K |
| 代理商： | VSC7105QF |
VSC7105/7106
VITESSE
Data Sheet
1.0625 Gbit/sec Transmitter/Receiver Chipset
for Fibre Channel or Proprietary Serial Links
Page 20
VITESSE Semiconductor Corporation
G52079-0 Rev. 2.7
Table 7: VSC7105 Pin Description
Pin #
44 PQFP
Name
Description
18-21,24-27
29-32,35-38
40-43
T00:19
INPUT - TTL
Parallel data on this bus is clocked in on the falling edge of TCLK in 20 bit mode, or on the
falling edge of both TCLK and TCLKN in 10 bit mode. T00 is transmitted rst in 20 bit
mode and T10 rst in 10 bit mode.
16
TEST
INPUT - Multi-Level Static Input
The level on this pin determines the serial encoding and the source of the bit clock to be
used. The table below lists the effects caused by driving TEST to various levels.
15
DWS
INPUT - Static: TTL
This pin selects the parallel data bus width. When LOW, a 20 bit parallel bus width is
selected and T00:19 are active. When HIGH, a 10 bit parallel data bus is selected, T10:19
are active and T00:09 are ignored.
2, 1
OE0
OE1
INPUT - TTL
Outputs enable inputs. Select serial output state as shown in the Table below.
13
REFCLK
CLOCK INPUT - Single-Ended (Biased at VDD/2, refer to Figure 14-A)
A free running reference clock for the PLL clock multiplier. The frequency of REFCLK is
0.1x the desired baud rate.
11, 10
TCLK
TCLKN
OUTPUTS - COMPLEMENTARY TTL
Half word rate clock true and complement (frequency = REFCLK/2). In the 10 bit parallel
data bus mode a new data word is clocked into the transmitter on the falling edge of both
TCLK and TCLKN. In the 20 bit parallel data bus mode a new data word is clocked into the
transmitter only on the falling edge of TCLK.
5,4
TLX+,
TLX-
OUTPUTS - DIFFERENTIAL Serial Output (Centered at VDD - 1.32V)
These outputs are functionally equivalent to TX+ and TX-.
Level
Effect
GND
PLL 10X Multiplied Clock used as bit clock and NRZ
encoding used. [Fibre Channel Compatible]
Tristate
Open
Test Mode where REFCLK input is used as bit clock and
NRZ encoding used
VDD
PLL 10X Multiplied Clock used as bit clock and NRZI
Encoding used.
OE0
OE1
TX+/TX-
TLX+/TLX-
LOW
active
LOW
HIGH
active
HIGH/LOW
HIGH
LOW
HIGH/LOW
active
HIGH
HIGH/LOW
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相關代理商/技術參數(shù) |
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|---|---|
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