參數(shù)資料
型號: VS46417801BTG-10
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 4M X 64 SYNCHRONOUS DRAM MODULE, 8 ns, DMA168
封裝: DIMM-168
文件頁數(shù): 30/30頁
文件大?。?/td> 295K
代理商: VS46417801BTG-10
Document:1G5-0134
Rev.2
Page 9
VIS
VS26417801B,VS46417801B
2M,4MX64-Bit
SDRAM Module
A.C Characteristics
Test Conditions : (Ta = 0 to 70°C VDD = 3.3V
, VSS = 0V)
AC input Levels(VIH/VIL)
2.4/0.4V
Input timing reference level/
Output timing reference leveel
1.4v
Input and fall time
1ns
Output load condition
50pF
Parameter
CAS
Latency
symbol
VS26417801B/VS46417801B
Unit
-8H
-8L
-10
Min
Max
Min
Max
Min
Max
CLK cycle time
3
tCK3
10
ns
2
tCK2
10
13
15
ns
CLK to valid output delay
3
tAC3
6
8
ns
2
tAC2
6
7
8
ns
CLK high pulse width
tCH
3
4
ns
CLK low pulse width
tCL
3
4
ns
CKE setup time
tCKS
2
3
ns
CKE hold time
tCKH
1
ns
Address setup time
tAS
2
3
ns
Address hold time
tAH
1
ns
Command setup time
tCMS
2
3
ns
Command hold time
tCMH
1
ns
Data - in setup time
tDS
2
3
ns
Data - in hold time
tDH
1
ns
Output data hold time
tOH
3
ns
CLK to output on low - Z
tLZ
0
ns
CLK to output in Hi - Z
tHZ
3
8
3
8
3
8
ns
Row active to active delay
tRRD
20
ns
RAS to CAS delay
tRCD
20
26
ns
Row precharge time
tRP
20
26
ns
Row active time
tRAS
50
120,000
50
120,000
60
120,000
ns
Row cycle time
tRC
70
86
ns
Last data in to burst stop
tBDL
1CLK
ns
Data - in to ACT (REF) command
(Auto Precharge)
tDAL
1CLK + tRP
ns
Data - in to precharge
tDPL
1 CLK
ns
Transition time
tT
1
10
1
10
1
10
ns
Mode reg. set cycle
tRSC
2 CLK
ns
Power down exit setup time
tPDE
8
ns
Self refresh exit time
tSRX
8
ns
Refresh time
tREF
32
ms
0.3V
±
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