參數(shù)資料
型號(hào)： VRS550-QLC25
廠商： Electronic Theatre Controls, Inc.
英文描述： VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
中文描述： VRS550 - 8KB閃存，256B的RAM，25MHz的，8位微控制器VRS560 - 16kB的閃存，256B的RAM，25MHz的，8位微控制器
文件頁(yè)數(shù)： 20/40頁(yè)
文件大小： 868K
代理商： VRS550-QLC25
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
20
Mode 1
For an operation in Mode 1, 10 bits are transmitted
through TXD or received through
transactions are composed of: a Start bit (Low), 8 data
bits (LSB first) and one Stop bit (high). The reception is
completed once the Stop bit sets the RB8 flag in the
SCON register. Either Timer 1 or Timer 2 controls the
baud rate in this mode.
The following diagram shows the serial port structure
when configured in Mode 1.
RXD. The
F
IGURE
18:
S
ERIAL
P
ORT
M
ODE
1
AND
3 B
LOCK
D
IAGRAM
Internal Bus
SBUF
D
S
Q
ZERO DETECTOR
CLK
1
Write to
SBUF
TX Control Unit
Start
TX Clock
Data
Send
RX Control Unit
RI
TI
RX Clock
Start
SHIFT
9-Bit Shift Register
SBUF
Internal Bus
READ SBUF
LOAD SBUF
Serial Port
Interrupt
Shift
Bit
Detector
÷16
÷16
1-Detector
RXD
÷2
Timer 2
Timer 1
Overflow
RCLK
TCLK
SMOD
0 1
0
1
0
1
Load
SBUF
Shift
TXD
Transmission in Mode 1
Transmission is initiated by any instruction that makes
use of SBUF as a destination register. The 9
th
bit
position of the transmit shift register is loaded by the
“write to SBUF” signal. This event also flags the TX
Control Unit that a transmission has been requested.
It is after the next rollover in the divide-by-16 counter
when transmission actually begins at T1 of the
machine cycle. It follows that the bit times are
synchronized to the divide-by-16 counter and not to the
“write to SBUF” signal.
When a transmission begins, it places the start bit at
TXD. Data transmission is activated one bit time later.
This activation enables the output bit of the transmit
shift register to TXD. One bit time after that, the first
shift pulse occurs.
In this mode, zeros are clocked in from the left as data
bits are shifted out to the right. When the most
significant bit of the data byte is at the output position
of the shift register, the 1 that was initially loaded into
the 9
th
position is to the immediate left of the MSB, and
all positions to the left of that contain zeros. This
condition flags the TX Control Unit to shift one more
time.
Reception in Mode 1
One to zero transitions at RXD initiate reception. It is
for this reason that RXD is sampled at a rate of 16
multiplied by the baud rate that has been established.
When a transition is detected, 1FFh is written into the
input shift register and the divide-by-16 counter is
immediately reset. The divide-by-16 counter is reset in
order to align its rollovers with the boundaries of the
incoming bit times.
In total, there are 16 states in the counter. During the
7
th
, 8
th
and 9
th
counter states of each bit time; the bit
detector samples the value of RXD. The accepted
value is the value that was seen in at least two of the
three samples. The purpose of doing this is for noise
rejection. If the value accepted during the first bit time
is not zero, the receive circuits are reset and the unit
goes back to searching for another one to zero
transition. All false start bits are rejected by doing this.
If the start bit is valid, it is shifted into the input shift
register, and the reception of the rest of the frame will
proceed.
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
arrives at the leftmost position in the shift register, (9-
bit register), it tells the RX control block to perform one
last shift operation: to set RI and to load SBUF and
RB8. The signal to load SBUF and RB8, and to set RI,
will be generated if, and only if, the following conditions
are met at the time the final shift pulse is generated:
-
Either SM2 = 0 or the received stop bit = 1
-
RI = 0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VRS550-QLI25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PAC25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PAI25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
VRS560-PLC25 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
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