參數(shù)資料
型號(hào): VRS550-QLC25
廠(chǎng)商: Electronic Theatre Controls, Inc.
英文描述: VRS550 - 8kB Flash, 256B RAM, 25MHz, 8-Bit MCU VRS560 - 16kB Flash, 256B RAM, 25MHz, 8-Bit MCU
中文描述: VRS550 - 8KB閃存,256B的RAM,25MHz的,8位微控制器VRS560 - 16kB的閃存,256B的RAM,25MHz的,8位微控制器
文件頁(yè)數(shù): 14/40頁(yè)
文件大?。?/td> 868K
代理商: VRS550-QLC25
VRS550 / VRS560
VERSA
Datasheet Rev 1.1
1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4
Tel: (514) 871-2447
http://www.goalsemi.com
14
Timer 0 / Timer1 Counter / Timer Functions
Timing Function
When operating as a timer, the counter is automatically
incremented at every machine cycle. A flag is raised in
the event that an overflow occurs and the counter
acquires a value of zero. These flags (TF0 and TF1)
are located in the TCON register.
T
ABLE
13:
T
IMER
0
AND
1 C
ONTROL
R
EGISTER
(TCON) –SFR 88
H
7
6
5
TF1
TR1
TF0
Bit
Mnemonic
Description
7
TF1
Timer 1 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
6
TR1
Timer 1 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
5
TF0
Timer 0 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware when processor vectors to
interrupt routine.
4
TR0
Timer 0 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
3
IE1
Interrupt Edge Flag. Set by hardware when
external interrupt edge is detected. Cleared
when interrupt processed.
2
IT1
Interrupt 1 Type Control Bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
1
IE0
Interrupt 0 Edge Flag. Set by hardware
when external interrupt edge is detected.
Cleared when interrupt processed.
0
IT0
Interrupt 0 Type control bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
Counting Function
4
3
IE1
2
IT1
1
IE0
0
IT0
TR0
When operating as a counter, the timer’s register is
incremented at every falling edge of the T0, T1 and T2
signals located at the input of the timer. In this case,
the signal is sampled at the T10 phase of each
machine cycle for Timer 0, Timer 1 and T9 for Timer 2.
When the sampler sees a high immediately followed by
a low in the next machine cycle, the counter is
incremented. Two machine cycles are required to
detect and record an event. This reduces the counting
frequency by a factor of 24 (24 times less than the
oscillator’s frequency).
Operating Modes
The user may change the operating mode by varying
the M1 and M0 bits of the TMOD SFR.
Mode 0
A schematic representation of this mode of operation
can be found below in Figure 10. From the figure, we
notice that the timer operates as an 8-bit counter
preceded by a divide-by-32 prescaler made of the
5LSB of TL1. The register of the counter is configured
to be 13 bits long. When an overflow causes the value
of the register to roll over to 0, the TFx interrupt signal
goes to 1. The count value is validated as soon as TRx
goes to 1 and the GATE bit is 0, or when INTx is 1.
F
IGURE
11:
T
IMER
/C
OUNTER
1 M
ODE
0: 13-B
IT
C
OUNTER
CLK
÷12
T1PIN
C/T =0
C/T =1
TR1
GATE
INT1 PIN
0
1
0
7
4
Mode 0
Mode 1
0
7
TL1
TF1
INT
TH1
CLK
Control
Mode 1
Mode 1 is almost identical to Mode 0. They differ in
that, in Mode 1, the counter uses the full 16-bits and
has no prescaler.
Mode 2
In this mode, the register of the timer is configured as
an 8-bit automatically re-loadable counter. In Mode 2, it
is the lower byte TLx that is used as the counter. In the
event of a counter overflow, the TFx flag is set to 1 and
the value contained in THx, which is preset by
software, is reloaded into the TLx counter. The value of
THx remains unchanged.
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