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VPX 3225D, VPX 3224D
PRELIMINARY DATA SHEET
59
Micronas
4.3.10.1. TTL Output Driver Description
The driving capability/strength is controlled by the state
of the two I
2
C registers F8
hex
and F9
hex
.
A special PVDD, PVSS supply is used only to support
the digital output pins. This means, inherently, that in
case of tri-state conditions, external sources should not
drive these signals above the voltage PVDD which sup-
plies the output pins.
All timing specifications are based on the following as-
sumptions:
– the load capacitance of the fast pins (output driver ty-
pe A) is C
A
= 30 pF,
– the load capacitance of the remaining pins (output
driver type B) is C
B
= 50 pF,
– no static currents are assumed,
– the driving capability of the pads is STR = 4, which
means that 5 of 8 output drivers are enabled.
The typical case specification relates to:
– the ambient temperature is T
A
= 25
°
C, which relates
to a junction temperature of T
J
= 70
°
C;
– the power supply of the pad circuits is PVDD = 3.3 V,
and the power supply of the digital parts is VDD =
5.0 V.
The best case specification relates to:
– a junction temperature of T
J
= 0
°
C,
– the power supply of the pad circuits is PVDD = 3.6 V,
and the power supply of the digital parts is VDD =
5.25 V.
The worst case specification relates to:
– a junction temperature of T
J
= 125
°
C,
– the power supply of the pad circuits is PVDD = 3.0 V,
and the power supply of the digital parts is VDD =
4.75 V.
Rise times are specified as a transition between 0.6 V to
2.4 V. Fall times are defined as a transition between
2.4 V to 0.6 V.
strength
0
strength
1
strength
2
strength
3
strength
4
strength
5
strength
6
strength = 7
Fig. 4–1:
Block diagram of the output stages
Note:
The drivers of the output pads are implemented
as a parallel connection of 8 tri-state buffers of the
same size. The buffers are enabled depending on the
desired driver strength. This opportunity offers the ad-
vantage of adapting the driver strength to on-chip and
off-chip constraints, e.g. to minimize the noise result-
ing from steep signal transitions.