
VPX 3220 A, VPX 3216 B, VPX 3214 C
PRELIMINARY DATA SHEET
MICRONAS INTERMETALL
33
I
2
C-Register Table
Name
Function
Mode
Number
of Bits
I
2
C Reg.
Address
Output Multiplexer
F0
8
w
Output FIFO
OFIFO
FIFO Control: (only available in Asynchronous Mode)
bit [4:0] : FIFO Flag – Half Full Level (interface signal HF)
hfull
bit [7:5] : Bus Shuffler
000
001,
010
011
100
101,
110
111
Meaning:
In[23:0] : Data from Color Space Stage
Out[23:0] : Data to Output FIFO
Out[23:0] = In[23:0]
Out[23:0] = In[7:0, 23:8]
Out[23:0] = In[15:0, 23:16]
Out[23:0] = In[15:8, 23:16, 7:0]
Out[23:0] = In[7:0, 15:8, 23:16]
Out[23:0] = In[23:16, 7:0, 15:8]
shuf
F1
8
w
Output Multiplexer
OMUX
vact
bit [1:0]: Port Mode
00
parallel_out, ’single clock’
Port A = FifoOut[23:16]
Port B = FifoOut[15:8];
01
’double clock’ (only available with a transport rate of 13.5 MHz)
Port A = FifoOut[23:16] / FifoOut[15:8],
Port B = FifoOut[7:0];
10,11reserved
mode
vact
bit [2] :
ASYNCHRONOUS MODE: Clock Slope (if Clock Source = external)
1
negative edge triggered
0
positive edge triggered.
SYNCHRONOUS MODE: Data Reset
1
set output ports to 0 during VACT(/FE#) = 0.
slope
vact
bit [3] :
Clock Source
1
Internal Source (Synchronous Mode) – PIXCLK is output
0
External Mode (Asynchronous Mode) – PIXCLK is input
clkio
direct
bit [5:4] : delay signal ’active video’ (signal FE) with respect to video output data.
Only available in Synchronous Mode.
00
no delay (default)
01
one clock cycle
10
two clock cycles
11
three clock cycles
delay
direct
bit [6] :
1
disable FIFO-Empty FE low pass filter
Only available in Asynchronous Mode.
bit [7] :
1
enable HLEN counter
hlen
The control register modes are
– w: write/read register
– d: register is double latched
– A: register is available only in VPX 3220 A; VPX 3216 B returns valid ACK, although no internal action is performed
– r:
– v: register is latched with vsync
read-only register
The mnemonics used in the Intermetall VPX demo software are given in the last column.