參數(shù)資料
型號(hào)： VPX3214
廠商： Electronic Theatre Controls, Inc.
英文描述： Video Pixel Decoders
中文描述： 視頻解碼器像素
文件頁(yè)數(shù)： 18/80頁(yè)
文件大?。?/td> 752K
代理商： VPX3214
PRELIMINARY DATA SHEET
VPX 3220 A, VPX 3216 B, VPX 3214 C
MICRONAS INTERMETALL
18
3. Video Timing
3.1. Video Reference Signals HREF and VREF
The VPX generates two video reference signals; a hori-
zontal reference (HREF) and a vertical reference
(VREF). These two signals are generated by program-
mable hardware and can be either free running or syn-
chronous to the analog input video. The video line stan-
dard (625/50 or 525/60) can be either inferred from the
analog input video or forced via I
2
C command from the
external controller. The polarity of the two signals is indi-
vidually selectable.
The circuitry which produces the VREF and HREF sig-
nals has been designed to provide a stable, robust set
of timing signals, even in the presence of erratic behav-
ior at the analog video input. Depending on the selected
operating mode, the period of the HREF and VREF sig-
nals are guaranteed to remain within a fixed range.
These video reference signals can therefore be used to
synchronize the external components of a video subsys-
tem (for example the neighboring ICs of a PC add-in
card).
3.1.1. HREF
Fig. 3–1 illustrates the timing of the HREF signal relative
to the analog input. The active period of HREF is fixed
and is always equal to the length of the active portion of
a video signal. Therefore, regardless of the video line
standard, HREF is active for 1056 periods of the 20.25
MHz system clock. The total period of the HREF signal
is expressed as
Φ
nominal
and depends on the video line
standard.
Φ
nominal
Analog
Video
Input
HREF
VPX
Delay
Fig. 3–1:
HREF relative to Input Video
52
μ
s
3.1.2. VREF
Figs. 3–2 and 3–3 illustrate the timing of the VREF signal
relative to field boundaries of the two TV standards. The
length of the VREF pulse is programmable in the range
between 2 and 9 video lines.
3.1.3. Odd/Even
Information on whether the current field is odd or even,
is supplied through the relationship between the edge
(either leading or trailing) of VREF and level of HREF.
This relationship is fixed and shown in Figs. 3–2 and
3–3. The same information can be supplied to the
FIELD/PREF pin. The polarity of the signal is program-
mable.
3.2. Operational Modes
The relationship between the video timing signals
(HREF and VREF) and the analog input video is deter-
mined by the selected operational mode. Three such
modes are available: the
Open Mode
, the
Forced
Mode
, and the
Scan Mode
. These modes are selected
via I
2
C commands from the external controller.
3.2.1. Open Mode
In the Open Mode, both the HREF and the VREF signal
track the analog video input. In the case of a change in
the line standard (i.e. switching between the video input
ports), HREF and VREF automatically synchronize to
the new input. When no video is present, both HREF and
VREF float to the idling frequency of their respective
PLLs. During changes in the video input (drop-out,
switching between inputs), the performance of the
HREF and VREF signals is not guaranteed.
3.2.2. Forced Mode
In the Forced Mode
,
VREF and HREF follow the input
video signal within certain tolerances. Dedicated hard-
ware is used to monitor the frequency of the analog tim-
ing. At the moment when the video signal exceeds the
allowed timing tolerances, generation of the timing sig-
nals is taken over by free running hardware. If the input
video is still present, the VPX continually attempts to re-
synchronize to it.
For each of the two video line standards (625/50 and
525/60), there exist normative values for the period of
both the HREF and VREF signals. Many analog input
signals deviate significantly from these norms (example,
consumer VCRs in their shuttle modes). In the Forced
Mode, monitoring hardware is used to impose an upper
boundary on the deviation. The maximum allowed hori-
zontal deviation is 24
μ
s. The upper boundary for verti-
cal deviation is
11% of the number of lines in the se-
lected line standard (625/50:
lines)
35 lines, 525/60:
30
During the free-running operation, video output data is
suppressed. If the VPX successfully resynchronizes,
video output resumes. The specific method used to sup-
press the output video depends on the transfer mode
(synchronous or asynchronous).
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PDF描述
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VPX3216B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Pixel Decoders
VPX3216B(PLCC44) 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Color Decoder Circuit
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