參數(shù)資料
型號: VL6524QOMH
廠商: 意法半導(dǎo)體
英文描述: VGA single-chip camera module
中文描述: 顯卡單芯片相機(jī)模塊
文件頁數(shù): 63/70頁
文件大小: 505K
代理商: VL6524QOMH
VL6524/VS6524
Electrical characteristics
63/70
13.4.4
Parallel data interface timing
VL6524/VS6524 contains a parallel data output port (D[7:0]) and associated qualification
signals (HSYNC, VSYNC, PCLK and FSO).
This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or
bit-serial output configurations. The port is disabled (high impedance) upon reset.
Figure 35.
Parallel data output video timing
Table 39.
13.5
ESD handling characteristics
Table 40.
Parallel data interface timings
Symbol
Description
Conditions
Min.
Typ.
Max.
Unit
f
PCLK
PCLK frequency
26
MHz
t
PCLKL
t
PCLKH
PCLK low width
10
ns
PCLK high width
10
ns
t
DV
PCLK to output valid
-5
5
ns
t
PCLKL
t
PCLKH
1/f
PCLK
PCLK
polarity = 0
D[0:7]
HSYNC
VSYNC
t
DV
Valid
ESD handling characteristics
Test
Criteria
Unit
ESD Machine Model
150
V
ESD Human body
1.5
kV
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