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參數(shù)資料
| 型號： | VL6524QOMH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | VGA single-chip camera module |
| 中文描述： | 顯卡單芯片相機模塊 |
| 文件頁數(shù)： | 20/70頁 |
| 文件大?。?/td> | 505K |
| 代理商： | VL6524QOMH |
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Output frame size control
VL6524/VS6524
20/70
6.1.2
Subsampling module
The VL6524/VS6524 has a built in sub-sampler which can divide the image by 1, 2, 3, 4, 5,
or 6.
Using the sub-sampler gives output images with reduced resolution but the same field of
view as the full VGA image or the region of interest defined in the cropping module.
Table 2
lists the available image sizes.
Table 2.
Subsampled images are produced by ‘dropping’ PCLKs so that only certain pixels are
qualified in the output data stream. The figure below indicates a portion of the PCLK
waveform for VGA and QVGA images. The effect of this is that the time aken to readout one
line of the image remains constant in all subsampled modes - it is just the number of clocks
that changes.
Figure 8.
PCLK waveform in subsampled modes
It is possible to use the crop module and the sub-sampler together to achieve almost any
required image size. When using the crop and subsampling functions together then the
number of lines in a frame must be an integer multiple of the subsample ratio.
6.2
Frame rate control
The VL6524/VS6524 features an extremely flexible frame rate controller. Using registers
uwDesiredFrame Rate_Num (MSB)
uwDesiredFrame Rate_Num (LSB)
and
bDesiredFrameRate_ Den
any desired frame rate between 1 and 30 fps can be selected
(see
Table 14: Frame rate control
for register description). To program a required frame rate
of 7.5 fps the numerator can be set to 15 and the denominator to 2. The default frame rate is
30 fps.
Slower frame rates are achieved by adding interframe lines. This results in a longer frame
period and therefore a longer period over which integration is possible. Due to the longer
Subsampled image sizes
Subsample ratio
Image format
Image dimensions
1 (default)
VGA
640 by 480
2
QVGA
320 by 240
3
-
213 by 160
4
QQVGA
160 by 120
5
SQCIF
128 by 96
6
-
106 by 80
D0
D3
D4
D[0:7]
VGA
QVGA
PCLK
D1
D2
D5
Pixel n
Pixel n+2
Pixel n+1
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