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參數(shù)資料
| 型號(hào)： | VG36256401A |
| 廠商： | Vanguard International Semiconductor Corporation |
| 英文描述： | CMOS Synchronous Dynamic RAM |
| 中文描述： | 同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器的CMOS |
| 文件頁(yè)數(shù)： | 1/69頁(yè) |
| 文件大?。?/td> | 944K |
| 代理商： | VG36256401A |
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Document : 1G5-0155 Rev.1
Page 1
VIS
VG36256401A
Preliminary VG36256801A
VG36256161A
CMOS Synchronous Dynamic RAM
Description
The device is CMOS Synchronous Dynamic RAM organized as 16,777,216 - word x 4 -bit x 4 - bank,
8,388,608 - word x 8 - bit x 4 - bank, or 4,194,304 - word x 16 - bit x 4 - bank. These various organizations
provide wide choice for different applications. It is designed with the state-of-the-art technology to meet stan-
dard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the perfor-
mance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
Single 3.3V (
) power supply
0.3V
High speed clock cycle time : 7.5ns/10ns
Fully synchronous with all signals referenced to a positive clock edge
Programmable CAS Iatency (2,3)
Programmable burst length (1,2,4,8,& Full page)
Programmable wrap sequence (Sequential/Interleave)
Automatic precharge and controlled precharge
Auto refresh and self refresh modes
Quad Internal banks controlled by A13 & A14 (Bank select)
Each Banks can operate simultaneously and independently
I/O level : LVTTL compatible
Random column access in every cycle
x4, x8, x16 organization
Input/Output controlled by DQM, LDQM, UDQM
8,192 refresh cycles/64ms
Burst termination by burst stop and precharge command
Burst read/single write option
The information shown is subject to change without notice.
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| VG36256801A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
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