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參數(shù)資料
| 型號： | VCXO-7050L-FREQ1-OUT21-DEVN1 |
| 元件分類： | XO, clock |
| 英文描述： | VCXO, CLOCK, 12.288 MHz - 33 MHz, CMOS OUTPUT |
| 文件頁數(shù)： | 1/1頁 |
| 文件大?。?/td> | 220K |
| 代理商： | VCXO-7050L-FREQ1-OUT21-DEVN1 |
I
I
Type
Frequency range
APR (Absolute Pull Range)
Operable temperature range
Storage temperature
Aging
Power supply voltage
Power supply current
Output load
Output level
Output symmetry
Rise time/Fall time
12.2880MHz to 80.0000MHz
2 (Vc
=
0.5~4.5V)
1
40
:
to
+
85
:
40
:
to
+
90
:
APR is tolerable with 20years aging
15mA max.
15pF
±
10%
V
OH
:
+
0.9Vcc
min. / V
OL
:
+
0.1Vcc max.
10ns max. / 10ns max.
MIL-STD-883 Method 2007
IEC68-2-6 test Fc
MIL-STD-202-Method 204
Vibration
Shock
Humidity
Weight
VCXO-7050
VCXO-7050L
±
50
×
10
–6
or
±
100
×
10
–6
±
50
×
10
–6
or
±
100
×
10
–6
2 (Vc
=
0.3~3.0V)
V
DD
=+
5.0V
±
5%
V
DD
=+
3.3V
±
5%
40% to 60% (at
+
2.50V DC)
40% to 60% (at
+
1.65V DC)
MIL-STD-883 Method 2002
IEC68-2-27 test Ea
MIL-STD-202-Method 213
EIA / JESD22-A101
0.17gram
APR
=
Absolute Pull Range is the minimum guaranteed (voltage contorolled) frequency shift ( f/f
NOM
)
over all conditions (temperature, aging, power supply and load)
1 33MHz to 80MHz are underdevelopment.
2 For 100
×
10
–6
, ask our sales representative.
5.08
2
4
1.8
2.54
VCXO-7050/7050L
I
“Small Size” as small as 0.063cc. (5
×
7
×
1.8mm)
Using 1 chip HCMOS IC.
3-state devices are available.
APR (Absolute Pull Range) of up to
±
50ppm or
±
100ppm
2.
I
I
#1
#2
#3
#4
#5
2.54
±
0.2
1
±
0
7.00
±
0.2
5
±
0
1
1
1
2
#6
1.40
(unit:mm)
PAD Function
#1:VC
#2:3-State
#3:GND
#4:OUT
#5:NC
#6:VDD
2.54
±
0.2
Dimensions(mm)
VCXO-7050/7050L
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