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參數(shù)資料
| 型號： | VC-709-PCIE2-100M000000 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 100 MHz, HSCL OUTPUT |
| 封裝： | ROHS COMPLIANT, HERMETIC SEALED, CERAMIC PACKAGE-6 |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 325K |
| 代理商： | VC-709-PCIE2-100M000000 |
Vectron International 267 Lowell Road, Hudson, NH 03051 Tel: 1-88-VECTRON-1 http://www.vectron.com
Page2
Performance Specifications
1. The VC-709 power supply pin should be filtered, e.g., a 0.1 and 0.01uf capacitor.
2. Contact factory for other frequencies.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Figure 1 defines the test circuit and Figure 2 defines these parameters.
5. Duty Cycle is defined as the On Time/Period.
6. Measured using an Agilent E5052.
7. Measured using a LeCroy Wavemaster 8600A, 90K samples.
8. Measured using a Wavecrest SIA3300C, 90K samples.
9. Outputs will be Enabled if the Enable/Disable pad is left open.
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical
Maximum
Units
Supply
Voltage
1
V
DD
2.375
3.165
2.5
3.3
2.625
3.465
30
V
V
Current (No Load)
I
DD
mA
Frequency
Nominal Frequency
2
Stability
3
(Ordering Options)
f
N
100.000
MHz
ppm
±50
Outputs
Output Logic Swing
V
OH
0.62
0.78
V
Output Rise and Fall Time
4
Rise Time
Fall Time
Load
Duty Cycle
5
Jitter (12 kHz - 20 MHz ) 100.000MHz
6
Period Jitter
7
RMS
P/P
Cycle-Cycle Jitter
7
RMS
P/P
Random Jitter
8
Deterministic Jitter
8
t
R
t
F
400
400
ps
ps
50 ohms to ground
50
0.2
45
55
0.4
%
ps
фJ
фJ
1.1
10.5
1.9
19.0
2.2
0
ps
ps
ps
ps
ps
ps
Enable/Disable
Output Enabled
8
Output Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temperature
Package Size
V
IH
V
IL
t
D
I
E/D
t
SU
T
OP
0.7*V
DD
0.3*V
DD
200
±200
2
V
V
ns
uA
ms
°C
mm
-10/70 or -40/85
5.0 x 7.0 x 1.8
t
R
t
F
V
AMP
*0.8
V
AMP
*0.2
Cross Point
On Time
Period
Figure 2.
V
AMP
Figure 1.
50 Ω
50 Ω
1
6
2
5
3
4
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