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| 型號(hào)： | V850E1 |
| 廠商： | NEC Corp. |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor Core |
| 中文描述： | 32位微處理器內(nèi)核 |
| 文件頁(yè)數(shù)： | 117/226頁(yè) |
| 文件大?。?/td> | 1709K |
| 代理商： | V850E1 |
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APPENDIX B INSTRUCTION LIST
203
User’s Manual U14559EJ3V1UM
Table B-1. Instruction Function List (in Alphabetical Order) (6/11)
Flag
Mnemonic
Operand
Format
CY
OV
S
Z
SAT
Instruction Function
OR
reg1, reg2
I
0
0/1
Or. ORs the word data of reg2 with the word
data of reg1, and stores the result in reg2.
ORI
imm16, reg1, reg2
VI
0
0/1
Or Immediate. ORs the word data of reg1 with
the 16-bit immediate data, zero-extended to
word length, and stores the result in reg2.
PREPARE
list12, imm5
XIII
Function Prepare. The general-purpose
register displayed in list12 is saved (4 is
subtracted from sp, and the data is stored in
that address). Next, the data is logically shifted
2 bits to the left, and the 5-bit immediate data
zero-extended to word length is subtracted
from sp.
PREPARE
list12, imm5,
sp/imm
XIII
Function Prepare. The general-purpose
register displayed in list12 is saved (4 is
subtracted from sp, and the data is stored in
that address). Next, the data is logically shifted
2 bits to the left, and the 5-bit immediate data
zero-extended to word length is subtracted
from sp. Then, the data specified by the third
operand is loaded to ep.
RETI
(None)
X
0/1
Return from Trap or Interrupt. Reads the
restored PC and PSW from the appropriate
system register, and restores from interrupt or
exception processing routine.
SAR
reg1, reg2
IX
0/1
0
0/1
Shift Arithmetic Right. Arithmetically shifts the
word data of reg2 to the right by ‘n’ positions,
where ‘n’ is specified by the lower 5 bits of
reg1 (the MSB prior to shift execution is copied
and set as the new MSB), and then writes the
result in reg2.
SAR
imm5, reg2
II
0/1
0
0/1
Shift Arithmetic Right. Arithmetically shifts the
word data of reg2 to the right by ‘n’ positions
specified by the lower 5-bit immediate data,
zero-extended to word length (the MSB prior to
shift execution is copied and set as the new
MSB), and then writes the result in reg2.
SASF
cccc, reg2
IX
Shift and Set Flag Condition. reg2 is logically
shifted left by 1, and its LSB is set to 1 in a
condition specified by condition code “cccc” is
satisfied; otherwise, LSB is set to 0.
相關(guān)PDF資料 |
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| V902-FREQ | VCXO, CLOCK, 65 MHz - 200 MHz, LVDS OUTPUT |
| V903-FREQ | VCXO, CLOCK, 200 MHz - 730 MHz, LVDS OUTPUT |
| VB-24STBU | POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.022A (COIL), 24VDC (COIL), 530mW (COIL), 5A (CONTACT), 150VDC (CONTACT), THROUGH HOLE-STRAIGHT MOUNT |
| VB-24STCU-5 | POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.022A (COIL), 24VDC (COIL), 530mW (COIL), 5A (CONTACT), 150VDC (CONTACT), THROUGH HOLE-STRAIGHT MOUNT |
| VB-24STCU-E | POWER/SIGNAL RELAY, DPDT, MOMENTARY, 0.022A (COIL), 24VDC (COIL), 530mW (COIL), 5A (CONTACT), 150VDC (CONTACT), THROUGH HOLE-STRAIGHT MOUNT |
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| V850E2FK4-H | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-bit Single-Chip Microcontroller |
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