參數(shù)資料
型號(hào): V62C31864L-35F
廠商: MOSEL-VITELIC
元件分類: SRAM
英文描述: 8K X 8 STANDARD SRAM, 35 ns, PDSO28
封裝: 0.330 INCH, SOP-28
文件頁數(shù): 9/12頁
文件大小: 68K
代理商: V62C31864L-35F
6
V62C31864 Rev. 1.6 August 1998
MOSEL VITELIC
V62C31864
AC Electrical Characteristics
(over all temperature ranges, VCC = 2.7V – 3.6V)
Read Cycle
Write Cycle
Parameter
Name
Parameter
-35
-70
Unit
Min.
Max.
Min.
Max.
tRC
Read Cycle Time
35
70
ns
tAA
Address Access Time
35
70
ns
tACS1
Chip Enable Access Time
35
70
ns
tACS2
Chip Enable Access Time
35
70
ns
tOE
Output Enable to Output Valid
15
30
ns
tCLZ1
Chip Enable to Output in Low Z
5—5—
ns
tCLZ2
Chip Enable to Output in Low Z
5—5—
ns
tOLZ
Output Enable to Output in Low Z
5—5—
ns
tCHZ
Chip Disable to Output in High Z
0
20
0
20
ns
tOHZ
Output Disable to Output in High Z
0
20
0
20
ns
tOH
Output Hold from Address Change
5—5—
ns
Parameter
Name
Parameter
-35
-70
Unit
Min.
Max.
Min.
Max.
tWC
Write Cycle Time
35
70
ns
tCW1
Chip Enable to End of Write
35
70
ns
tCW2
Chip Enable to End of Write
35
70
ns
tAS
Address Setup Time
0—0—
ns
tAW
Address Valid to End of Write
35
70
ns
tWP
Write Pulse Width
25
50
ns
tWR
Write Recovery Time
0—0—
ns
tWHZ
Write to Output High-Z
0
20
0
25
ns
tDW
Data Setup to End of Write
25
30
ns
tDH
Data Hold from End of Write
0—0—
ns
tOW
Output Active from End of Write
5—5—
ns
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