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參數(shù)資料
| 型號(hào)： | V62C31864L-35F |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | SRAM |
| 英文描述： | 8K X 8 STANDARD SRAM, 35 ns, PDSO28 |
| 封裝： | 0.330 INCH, SOP-28 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | V62C31864L-35F |
2
V62C31864 Rev. 1.6 August 1998
MOSEL VITELIC
V62C31864
Pin Descriptions
A0–A12
Address Inputs
These 13 address inputs select one of the 8,192 x 8
bit segments in the RAM.
CE1, CE2 Chip Enable Inputs
CE1 is active LOW and CE2 is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The Output Enable input is active LOW. When OE
is LOW with CE1 LOW, CE2 HIGH, and WE HIGH,
data of the selected memory location will be
available on the I/O pins. When OE is HIGH, the I/O
pins will be in the high impedance state.
WE
Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE1 and WE inputs are
both LOW with CE2 HIGH, the data present on the
I/O pins will be written into the selected memory
location.
I/O0–I/O7 Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
VCC
Power Supply
GND
Ground
Pin Configurations (Top View)
28-Pin SOP
28-Pin TSOP (Standard)
VCC
A8
A9
A11
A10
OE
I/O0
I/O1
I/O2
GND
A0
A1
A2
A3
A4
A5
I/O7
I/O6
I/O5
I/O4
51864 02
CE2
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A6
A7
I/O3
CE1
OE
A11
A9
A8
CE2
WE
VCC
NC
A12
A7
A6
A5
A4
A3
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
51864 03
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