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| 型號(hào)： | V62/05616-01XE |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.2 A SWITCHING CONTROLLER, 1150 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | GREEN, PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 17/21頁(yè) |
| 文件大小： | 447K |
| 代理商： | V62/05616-01XE |
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SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010
Electrical Characteristics
TA = –40°C to 125°C for Q temperature and TA = –55°C to 125°C for M temperature, RT = 3.65 k, CT = 1 nF, VCC = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Reference, VREF
VO
Output voltage range
TJ = 25°C, IO = 1 mA
5.05
5.1
5.15
V
Line regulation
12 V
≤ VCC ≤ 20 V
2
15
mV
Load regulation
1 mA
≤ IO ≤ 10 mA
5
20
mV
Total output variation
Line, load, temperature
5.03
5.17
V
Temperature stability(1)
T(min) < TA < T(max)
0.2
0.4
mV/°C
Output noise voltage(1)
10 Hz < f < 10 kHz
50
mVRMS
Long-term stability(1)
TJ = 125°C, 1000 h
5
25
mV
Short-circuit current
VREF = 0 V
30
60
90
mA
Oscillator
TJ = 25°C
375
400
425
kHz
fOSC
Initial accuracy(1)
RT = 6.6 k, CT = 220 pF, TA = 25°C
0.9
1
1.1
MHz
Line, temperature
350
450
kHz
Total variation(1)
RT = 6.6 k, CT = 220 pF
0.85
1.15
MHz
Voltage stability
12 V
≤ VCC ≤ 20 V
1%
Temperature stability(1)
T(min) < TA < T(max)
5%
High-level output voltage, clock
3.7
4
V
Low-level output voltage, clock
0
0.2
V
Ramp peak
2.6
2.8
3
V
Ramp valley
0.7
1
1.25
V
Ramp valley to peak
1.6
1.8
2
V
IOSC
Oscillator discharge current
RT = OPEN, VCT = 2 V
9
10
11
mA
Error Amplifier
Input offset voltage
2
10
mV
Input bias current
0.6
3
mA
Input offset current
0.1
1
mA
Open-loop gain
1 V < VO < 4 V
60
95
dB
CMRR
Common-mode rejection ratio
1.5 V < VCM < 5.5 V
75
95
dB
PSRR
Power-supply rejection ratio
12 V < VCC < 20 V
85
110
dB
IO(sink)
Output sink current
VEAOUT = 1 V
1
2.5
mA
IO(src)
Output source current
VEAOUT = 4 V
–1.3
–0.5
mA
High-level output voltage
IEAOUT = –0.5 mA
4.5
4.7
5
V
Low-level output voltage
IEAOUT = –1 mA
0
0.5
1
V
Gain bandwidth product
f = 200 kHz
6
12
MHz
Slew rate(1)
6
9
V/ms
PWM Comparator
IBIAS
Bias current, RAMP
VRAMP = 0 V
–1
–8
mA
Minimum duty cycle
0%
Maximum duty cycle
85%
tLEB
Leading-edge blanking time
RLEB = 2 k, CLEB = 470 pF
300
375
450
ns
RLEB
Leading-edge blanking resistance
VCLK/LEB = 3 V
8.5
10
11.5
k
VZDC
Zero dc threshold voltage, EAOUT
VRAMP = 0 V
1.1
1.25
1.4
V
tDELAY
Delay-to-output time(1)
VEAOUT = 2.1 V, VILIM = 0-V to 2-V step
50
80
ns
(1)
Specified by design. Not production tested.
Copyright 2005–2010, Texas Instruments Incorporated
5
Product Folder Link(s): UC2825A-EP
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