- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄202172 > V55C2256164VBT10I (PROMOS TECHNOLOGIES INC) 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 PDF資料下載
參數(shù)資料
| 型號(hào)： | V55C2256164VBT10I |
| 廠(chǎng)商： | PROMOS TECHNOLOGIES INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 2/46頁(yè) |
| 文件大?。?/td> | 575K |
| 代理商： | V55C2256164VBT10I |
第1頁(yè)當(dāng)前第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)
10
V55C2256164VB Rev. 1.2 May 2007
ProMOS TECHNOLOGIES
V55C2256164VB
Burst Length and Sequence:
Refresh Mode
SDRAM has two refresh modes, Auto Refresh
and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.
The chip enters the Auto Refresh mode, when
RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re-
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.
The chip has an on-chip timer and the Self Re-
fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
tion. After the exit command, at least one tRC delay
is required prior to any access command.
DQM Function
DQM has two functions for data I/O read and
write operations. During reads, when it turns to
“high” at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency tDQZ ). It also provides
a data mask function for writes. When DQM is acti-
vated, the write operation at the next clock is prohib-
ited (DQM Write Mask Latency tDQW = zero clocks).
Power Down
In order to reduce standby power consumption, a
power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir-
cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera-
tions, therefore the device can’t remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak-
ing CKE “high”. One clock delay is required for
mode entry and exit.
Auto Precharge
Two
methods
are
available
to
precharge
SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command
is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the
precharge operation one clock before the last data
out for CAS latencies 2, two clocks for CAS laten-
cies 3 and three clocks for CAS latencies 4. If CA10
is high when a Write Command is issued, the Write
a data mask function for writes. When DQM is
Burst
Length
Starting Address
(A2 A1 A0)
Sequential Burst Addressing
(decimal)
Interleave Burst Addressing
(decimal)
2
xx0
xx1
0, 1
1, 0
0, 1
1, 0
4x00
x01
x10
x11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
8
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Full Page
nnn
Cn, Cn+1, Cn+2
Not supported
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V55C3256164VGLK-10IPC | SYNCHRONOUS DRAM, PBGA54 |
| V55C3256164VGLK-7HPC | SYNCHRONOUS DRAM, PBGA54 |
| V580MC04 | VCO, 850 MHz - 890 MHz |
| V707S001 | VCO, 500 MHz - 1000 MHz |
| V706S001 | VCO, 600 MHz - 1200 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V55HD | 制造商:Bugera 功能描述:55 WATT GUITAR AMPLIFIER 2 CHANNEL TUBE HEAD |
| V55MLA0402LN | 制造商:LITTELFUSE 制造商全稱(chēng):Littelfuse 功能描述:Varistor Products Surface Mount Multilayer Varistors (MLVs) > MLA Series |
| V55MLA0402N | 制造商:LITTELFUSE 制造商全稱(chēng):Littelfuse 功能描述:Varistor Products Surface Mount Multilayer Varistors (MLVs) > MLA Series |
| V55MLA0603H | 制造商:Littelfuse 功能描述: |
| V55MLA0603LN4 | 制造商:LITTELFUSE 制造商全稱(chēng):Littelfuse 功能描述:Varistor Products Surface Mount Multilayer Varistors (MLVs) > MLA Series |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。