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參數(shù)資料
| 型號： | V23806-A8-C1 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | Multimode 1300 nm LED Fast Ethernet/FDDI/ATM 10 dB 155 MBd 1x9 Transceiver |
| 中文描述： | 多模1300納米發(fā)光快速以太網(wǎng)/光纖分布式數(shù)據(jù)介面/ ATM的10分貝，155 MBd的1x9收發(fā)器 |
| 文件頁數(shù)： | 3/3頁 |
| 文件大小： | 262K |
| 代理商： | V23806-A8-C1 |
Infineon Technologies AG i.Gr. Fiber Optics Wernerwerkdamm 16 Berlin D-13623, Germany
Infineon Technologies, Corp. Fiber Optics 19000 Homestead Road Cupertino, CA 95014 USA
Siemens K.K. Fiber Optics Takanawa Park Tower 20-14, Higashi-Gotanda, 3-chome, Shinagawa-ku Tokyo 141, Japan
www.infineon.com/fiberoptics
Receiver Electro-Optical Characteristics
Notes
1. For a bit error rate (BER) of less than 1x10
E–12
over a receiver eye
opening of least 1.5 ns. Measured with a 2
7
–1 PRBS at 194 MBd.
2. For a BER of less than 1x10
E-12
. Measured in the center of the eye
opening with a 2
7
-1 PRBS at 194 MBd.
3. Measured at an average optical power level of –20 dBm with a
62.5 MHz square wave.
4. All jitter values are peak-to-peak. RX output jitter requirements are
not considered in the ATM standard draft. In general the same
requirements as for FDDI are met.
5. Measured at an average optical power level of –20 dBm.
6. Measured at –33 dBm average power.
7 An increase in optical power through the specified level will
cause the SIGNAL detect output to switch from a Low state to
a High state.
8. A decrease in optical power through the specified level will
cause the SIGNAL detect output to switch from a High state to
a Low state.
9. PECL compatible. Load is 50
into V
CC
–2 V. Measured under DC
conditions. For dynamic measurements a tolerance of 50 mV should
be added for V
CC
=+5 V.
Pin Description
APPLICATION NOTE
Multimode 1300nm ATM 1x9 Transceiver
The power supply filtering is required for good EMI perfor-
mance. Use short tracks from the inductor L1/L2 to the module
V
CC
–Rx/V
CC
–Tx.
A GND plane under the module is recommended for good EMI
and sensitivity performance as well as ground connection of
studs.
Receiver
Symbol
Min.
Typ.
Max.
Units
Data Rate
DR
5
200
MBd
Sensitivity
Average Power)
(1)
P
IN
–33
–31
dBm
Saturation (Average
Power)
(2)
P
SAT
–14
–11
Duty Cycle
Distortion
(3, 4)
Deterministic Jitter
(4, 5)
t
DJ
Random Jitter
(4, 6)
t
DCD
1.4
ns
2.2
t
RJ
P
SDA
2.3
Signal Detect
Assert Level
(7)
–42.5
–30
dBm
Signal Detect
Deassert Level
(8)
P
SDD
–45
–31.5
Signal Detect
Hysteresis
Output Low Voltage
(9)
Output High Voltage
(9)
P
SDA
–
P
SDD
V
OL
–V
CC
V
OH
–V
CC
–1025
t
R
, t
F
1.5
dB
–1810
–1620
mV
–880
Output Data
Rise/Fall Time,
20%–80%
1.3
ns
Output SD
Rise/Fall Time,
20%–80%
40
Pin Name
Level/Logic
Pin#
Description
R
x
V
EE
Rx Ground Power Supply 1
Negative power sup-
ply, normally ground
RD
Rx Output
Data
PECL Output
2
Receiver output data
RDn
3
Inverted receiver out-
put data
RxSD
RX Signal
Detect
PECL Output
active high
4
High level on this out-
put shows there is an
optical signal.
R
x
V
CC
Rx +5 V
T
x
V
CC
TxDn
Power Supply 5
Positive power sup-
ply, +5 V
Tx +5 V
6
Tx Input
Data
PECL Input
7
Inverted transmitter
input data
TxD
8
Transmitter input
data
T
x
V
EE
Tx Ground Power Supply 9
Negative power sup-
ply, normally ground
Stud
Ground
S1/
S2
Ground connected,
Mech. support
GND
C1
VCC
VCC
GND
C2
VCC Rx
L1
GND
C3
GND
C4
L2
VCC Tx
GND
GND
VCC-Tx
VCC-Rx
Transceiver
R
R
GNDGND
VCC
-
Tx
GNDGND
VCC
-
Rx
GND
9
1
R
R
R
R
R
R
R
TxD
TxDn
RDn
SD
RD
GND
GND
DC coupling between ECL gates.
C1/3= 4700 nF (optional)
C2/4= 4700 nF
L1/2= 15000 nH
(L2 is optional)
R in
R1/3
+5 V
82
R2/4
130
R5/7
82
R6/8
130
R9
200
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