參數(shù)資料
型號(hào): USB1T1105AMHX
廠商: Fairchild Semiconductor
文件頁(yè)數(shù): 5/12頁(yè)
文件大小: 0K
描述: TRANSCEIVER USB W/VREG 16MHBCC
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: USB 2.0
電源電壓: 4 V ~ 5.5 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-MLP,16-MHBCC
供應(yīng)商設(shè)備封裝: 16-MLP
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 1223 (CN2011-ZH PDF)
其它名稱(chēng): USB1T1105AMHXDKR
www.fairchildsemi.com
2
USB1
T1
1
0
5
A
Connection Diagram
(Bottom View)
Terminal Descriptions
Terminal
Number
Terminal
Name
I/O
Terminal Description
1OE
I
Output Enable: Active LOW enables the transceiver to transmit data on the bus. When
not active the transceiver is in the receive mode (CMOS level is relative to VCCIO)
2
RCV
O
Receive Data Output: Non-inverted CMOS level output for USB differential Input (CMOS
output level is relative to VCCIO). Driven LOW when SUSPN is HIGH;
RCV output is stable and preserved during SE0 condition.
3Vp
O
Single-ended D
receiver output VP (CMOS level relative to VCCIO):
Used for external detection of SEO, error conditions, speed of connected device;
Driven HIGH when no supply connected to VCC and VREG.
4Vm
O
Single-ended D
receiver output Vm (CMOS level relative to VCCIO):
Used for external detection of SEO, error conditions, speed of connected device;
Driven HIGH when no supply connected to VCC and VREG.
5
SUSPND
I
Suspend:
Enables a low power state (CMOS level is relative to VCCIO). While the SUSPND pin is
active (HIGH) it will drive the RCV pin to logic “0” state.
6
MODE
I
MODE input (CMOS level is relative to VCCIO). A HIGH selects the differential input
MODE (Vpo, Vmo) whereas a LOW enables the single-ended MODE (Vo, VFSEO) see
Table 2 and Table 3
7VCCIO
Supply Voltage for digital I/O pins (1.65V to 3.6V):
When not connected the D
and D pins are in 3-STATE. This supply bus is totally
independent of VCC (5V) and VREG (3.3V).
8NC
NC
10, 9
D
, D
AI/O
Data
, Data : Differential data bus conforming to the USB standard.
11
Vpo / Vo
I
Driver Data Input (CMOS level is relative to VCCIO); Schmitt trigger input;
see Table 2 and Table 3
12
Vmo / FSEO
I
Driver Data Input (CMOS level is relative to VCCIO); Schmitt trigger input;
see Table 2 and Table 3
13
VREG (3.3V)
Internal Regulator Option:
Regulated supply output voltage (3.0V to 3.6V) during 5V operation;
decoupling capacitor of at least 0.1
PF is required.
14
VCC (5.0V)
Internal Regulator Option:
Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB line
Vbus.
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