參數(shù)資料
型號: UPD9903
廠商: NEC Corp.
元件分類: Codec
英文描述: UPD9903 ANALOG SUBSCRIBER LINE LSI DIGITAL CODEC
中文描述: UPD9903模擬用戶線數(shù)字編解碼器大規(guī)模集成電路
文件頁數(shù): 9/28頁
文件大?。?/td> 135K
代理商: UPD9903
μ
PD9903
9
(2) AC conditions
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Units
Data clock frequency
f
DCLK
(= 1/t
CY
)
±
50 ppm
2048
kHz
Data clock pulse width
t
DCLK
200
ns
Frame sync clock frequency
f
S
±
50 ppm
8.0
kHz
High level frame sync pulse
width
t
WHS
t
CY
×
8
ns
Low level frame sync pulse
width
t
WLS
t
CY
×
8
ns
Clock rise time
t
R
30
ns
Clock fall time
t
F
30
ns
Float in sync timing
t
CSD1
100
ns
t
CSD2
40
ns
High level width of frame
sync clock and data clock
t
WHSC
100
ns
HW
R
set-up time
t
DSR
Note 1
65
ns
HW
R
hold time
t
DHR
Note 1
120
ns
Minimum width of reset pulse
PW
RST
RST pin
Note 2
10
μ
s
Notes 1.
During timing measurement, use 5 ns as the rise time and fall time for the digital input wave form and
clock signal.
2.
The
μ
PD9903 is initialized when high level input is applied to the RST pin after applying low level input
for several clock widths. (However, use of the RST pin is not guaranteed during low level input. Also,
low level input alone does not initialize the
μ
PD9903.)
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