
μ
PD9611
4
1. PIN DESCRIPTION
Pin No.
Symbol
I/O
Name and Function
1
A
IN
1
I
Transmit analog input pin for channel 1
When not used, connect to ACOM
OUT
1 pin.
2
A
OUT
1
O
Receive analog output pin for channel 1
3
NC
–
Leave this pin open.
4
A
IN
2
I
Receive analog input pin for channel 2
When not used, connect to ACOM
OUT
1 pin.
5
A
OUT
2
O
Transmit analog output pin for channel 2
6
NC
–
Leave this pin open.
7
ACOM
IN
1
I
Signal reference voltage input for channel 1
8
ACOM
OUT
1
O
Signal reference voltage output for channel 1
9
IN
2
I
Signal reference voltage input for channel 2
10
ACOM
OUT
2
O
Signal reference voltage output for channel 2
11
AV
DD
1
–
Analog power supply pin for channel 1
+5
±
0.25 V
12
AV
DD
2
–
Analog power supply pin for channel 2
+5
±
0.25 V
13
AV
DD
3
–
Analog power supply pin for channel 3
+5
±
0.25 V
14
AV
DD
4
–
Analog power supply pin for channel 4
+5
±
0.25 V
15
DV
DD
–
Digital power supply pin
+5
±
0.25 V
16
NC
–
Leave this pin open.
17
PD1
I
Power-down control input pin for channel 1
Channel 1 enters power-down mode when this signal is low level.
The output of D
X
pin for channel 1 becomes high-impedance and A
OUT
1 becomes
signal reference voltage in the power-down mode.
18
PD2
I
Power-down control input pin for channel 2
Channel 2 enters power-down mode when this signal is low level.
The output of D
X
pin for channel 2 becomes high-impedance and A
OUT
2 becomes
signal reference voltage in the power-down mode.
19
PD3
I
Power-down control input pin for channel 3
Channel 3 enters power-down mode when this signal is low level.
The output of D
X
pin for channel 3 becomes high-impedance and A
OUT
3 becomes
signal reference voltage in the power-down mode.
20
PD4
I
Power-down control input pin for channel 4
Channel 4 enters power-down mode when this signal is low level.
The output of D
X
pin for channel 4 becomes high-impedance and A
OUT
4 becomes
signal reference voltage in the power-down mode.
21
FSC
I
Frame synchronous clock input pin (8 kHz)
22
DCLK
I
Data clock input pin (2048 kHz)
23
D
X
O
Transmit PCM data output pin
This pin outputs PCM data for channel 1 to 4 in synchronization with rising edges
of DCLK after rising edges of FSC. It becomes high-impedance for other timings.
24
D
R
I
Receive PCM data input pin
This pin inputs PCM data for channel 1 to 4 in synchronization with falling edges of
DCLK after rising edges of FSC.
25
SP
CLK
I
Setting data clock input pin
26
SP
SYNC
I
Setting synchronous clock input pin
27
SP
DATA
I
Setting data input pin