參數(shù)資料
型號(hào)： UPD8891
廠商： NEC Corp.
英文描述： (5340 x 5340) PIXELS x 3 + 2670 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
中文描述： （5340 x 5340）像素× 3 2670像素× 3彩色CCD線性圖像傳感器
文件頁(yè)數(shù)： 6/32頁(yè)
文件大?。?/td> 297K
代理商： UPD8891
Data Sheet S16039EJ2V0DS
6
μ
PD8891
ABSOLUTE MAXIMUM RATINGS (T
A
=
+
25
°
C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
V
OD
0.3 to
+
15
V
Shift register clock voltage
V
φ
1-300
, V
φ
1-1200
, V
φ
1L
,
0.3 to
+
8
V
V
φ
2-300
, V
φ
2-1200
, V
φ
2L
Reset gate clock voltage
V
φ
RB
0.3 to
+
8
V
Reset feed-through level clamp
clock voltage
V
φ
CLB
0.3 to
+
8
V
300/1200 dpi select signal voltage
V
φ
SEL
0.3 to
+
8
V
Transfer gate clock voltage
Operating ambient temperature
Note
V
φ
TG1
to V
φ
TG3
0.3 to
+
8
V
T
A
0 to
+
60
°
C
Storage temperature
T
stg
40 to
+
70
°
C
Note
Use at the condition without dew condensation.
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+
25
°
C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
V
OD
11.4
12.0
12.6
V
Shift register clock high level
V
φ
1-300H
, V
φ
1-1200H
, V
φ
1LH
,
4.75
5.0
5.25
V
V
φ
2-300H
, V
φ
2-1200H
, V
φ
2LH
Shift register clock low level
V
φ
1-300L
, V
φ
1-1200L
, V
φ
1LL
,
0.3
0
+
0.25
V
V
φ
2-300L
, V
φ
2-1200L
, V
φ
2LL
Reset gate clock high level
V
φ
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
φ
RBL
0.3
0
+
0.5
V
Reset feed-through level clamp clock
high level
V
φ
CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock
low level
V
φ
CLBL
0.3
0
+
0.5
V
300/1200 dpi select signal high level
V
φ
SELH
4.5
5.0
5.5
V
300/1200 dpi select signal low level
V
φ
SELL
0.3
0
+
0.5
V
Transfer gate clock high level
V
φ
TG1H
to V
φ
TG3H
4.75
V
φ
1-300H
,
V
φ
1-1200H
Note
V
φ
1-300H
,
V
φ
1-1200H
Note
V
Transfer gate clock low level
V
φ
TG1L
to V
φ
TG3L
0.3
0
+
0.15
V
Data rate
f
φ
RB
2.0
5.0
MHz
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than shift register clock high level (V
φ
1-300H
,
V
φ
1-1200H
), image lag can increase.
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