18
User’s Manual U13952EJ3V1UD
LIST OF FIGURES (3/5)
Figure No.
Title
Page
10-12
AVDD Pin Processing ..................................................................................................................................152
11-1
Block Diagram of 10-Bit A/D Converter ......................................................................................................154
11-2
Format of A/D Converter Mode Register 0 .................................................................................................156
11-3
Format of A/D Input Selection Register 0 ...................................................................................................157
11-4
Basic Operation of 10-Bit A/D Converter ....................................................................................................159
11-5
Relationship Between Analog Input Voltage and A/D Conversion Result...................................................160
11-6
Software-Started A/D Conversion...............................................................................................................161
11-7
How to Reduce Current Consumption in Standby Mode ............................................................................162
11-8
Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ..................................163
11-9
Conversion Result Readout Timing (When Conversion Result Is Normal Value) .......................................163
11-10
Analog Input Pin Processing ......................................................................................................................164
11-11
A/D Conversion End Interrupt Request Generation Timing ........................................................................165
11-12
AVDD Pin Processing ..................................................................................................................................165
12-1
Block Diagram of Comparator ....................................................................................................................167
12-2
Format of Comparator Mode Register 0 .....................................................................................................168
12-3
Settings of Comparator Mode Register 0 for Comparator Operation..........................................................169
12-4
Settings of External Interrupt Mode Register 1 at INTCMP0 Occurrence...................................................169
12-5
Comparator Operation Timing ....................................................................................................................170
13-1
Block Diagram of Serial Interface 00 ..........................................................................................................173
13-2
Block Diagram of Baud Rate Generator .....................................................................................................174
13-3
Format of Serial Operation Mode Register 00 ............................................................................................176
13-4
Format of Asynchronous Serial Interface Mode Register 00 ......................................................................177
13-5
Format of Asynchronous Serial Interface Status Register 00 .....................................................................179
13-6
Format of Baud Rate Generator Control Register 00 .................................................................................180
13-7
Format of Asynchronous Serial Interface Transmit/Receive Data ..............................................................191
13-8
Asynchronous Serial Interface Transmission Completion Interrupt Timing.................................................193
13-9
Asynchronous Serial Interface Reception Completion Interrupt Timing......................................................194
13-10
Receive Error Timing..................................................................................................................................195
13-11
3-Wire Serial I/O Mode Timing ...................................................................................................................201
14-1
Block Diagram of LCD Controller/Driver .....................................................................................................204
14-2
Format of LCD Display Mode Register 0 ....................................................................................................205
14-3
Format of LCD Port Selector 0 ...................................................................................................................206
14-4
Format of LCD Clock Control Register 0 ....................................................................................................207
14-5
Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs ...................208
14-6
Common Signal Waveforms .......................................................................................................................211
14-7
Voltages and Phases of Common and Segment Signals ...........................................................................212
14-8
Examples of LCD Drive Power Connections (with On-Chip Voltage Divider Resistors) .............................214
14-9
Static LCD Display Pattern and Electrode Connections .............................................................................215
14-10
Example of Connecting Static LCD Panel ..................................................................................................216
14-11
Static LCD Drive Waveform Examples .......................................................................................................217