
User
’s Manual U14186EJ6V0UD
13
3.2.15
VPP (flash memory version only) ................................................................................................... 51
3.2.16
IC0 (mask ROM version only)....................................................................................................... 51
3.2.17
IC3 ............................................................................................................................................... 51
3.3
Pin I/O Circuits and Recommended Connection of Unused Pins.........................................52
CHAPTER 4 PIN FUNCTIONS (
PD789167Y AND 789177Y SUBSERIES)....................................54
4.1
Pin Function List ........................................................................................................................54
4.2
Description of Pin Functions ....................................................................................................56
4.2.1
P00 to P05 (Port 0) ....................................................................................................................... 56
4.2.2
P10, P11 (Port 1) .......................................................................................................................... 56
4.2.3
P20 to P26 (Port 2) ....................................................................................................................... 56
4.2.4
P30 to P33 (Port 3) ....................................................................................................................... 57
4.2.5
P50 to P53 (Port 5) ....................................................................................................................... 57
4.2.6
P60 to P67 (Port 6) ....................................................................................................................... 58
4.2.7
RESET.......................................................................................................................................... 58
4.2.8
X1, X2........................................................................................................................................... 58
4.2.9
XT1, XT2 ...................................................................................................................................... 58
4.2.10
AVDD ............................................................................................................................................ 58
4.2.11
AVSS ............................................................................................................................................. 58
4.2.12
AVREF ........................................................................................................................................... 58
4.2.13
VDD0, VDD1 .................................................................................................................................... 58
4.2.14
VSS0, VSS1 ..................................................................................................................................... 58
4.2.15
VPP (flash memory version only) ................................................................................................... 59
4.2.16
IC0 (mask ROM version only)....................................................................................................... 59
4.2.17
IC2 ................................................................................................................................................ 59
4.3
Pin I/O Circuits and Recommended Connection of Unused Pins.........................................60
CHAPTER 5 CPU ARCHITECTURE ......................................................................................................62
5.1
Memory Space ............................................................................................................................62
5.1.1
Internal program memory space ................................................................................................... 65
5.1.2
Internal data memory (internal high-speed RAM) space............................................................... 66
5.1.3
Special-function register (SFR) area............................................................................................. 66
5.1.4
Data memory addressing.............................................................................................................. 66
5.2
Processor Registers ..................................................................................................................69
5.2.1
Control registers ........................................................................................................................... 69
5.2.2
General-purpose registers ............................................................................................................ 72
5.2.3
Special-function registers (SFR) ................................................................................................... 73
5.3
Instruction Address Addressing ..............................................................................................76
5.3.1
Relative addressing ...................................................................................................................... 76
5.3.2
Immediate addressing .................................................................................................................. 77
5.3.3
Table indirect addressing.............................................................................................................. 78
5.3.4
Register addressing...................................................................................................................... 78
5.4
Operand Address Addressing ..................................................................................................79
5.4.1
Direct addressing.......................................................................................................................... 79
5.4.2
Short direct addressing................................................................................................................. 80