
APPENDIX D
REVISION HISTORY
User’s Manual U14186EJ6V0UD
461
(2/3)
Edition
Revision from Previous Edition
Applied to:
Addition of 9.5 (4) Cautions when set to STOP mode
Addition of 9.5 (5) Start timing of external event counter
CHAPTER 9 8-BIT TIMER/EVENT
COUNTERS 80 TO 82
Addition of 12.5 (8) Input impedance of ANI0 to ANI7 pins
CHAPTER 12 8-BIT A/D CONVERTER
(
PD789167 AND 789167Y
SUBSERIES)
Modification of description in 13.2 (2) A/D conversion result register 0
(ADCR0)
Modification of Figure 13-4 Basic Operation of 10-Bit A/D Converter
Addition of 13.5 (8) Input impedance of ANI0 to ANI7 pins
CHAPTER 13 10-BIT A/D
CONVERTER (
PD789177 AND
789177Y SUBSERIES)
Modification of Figure 14-1 Block Diagram of Serial Interface 20
Modification of description on PE20 flag in Figure 14-5 Format of
Asynchronous Serial Interface Status Register 20
Addition of 14.4.2 (2) (f) Reading receive data
CHAPTER 14 SERIAL INTERFACE 20
Overall revision of description on flash memory programming
CHAPTER 20 FLASH MEMORY
VERSION
Addition of electrical specifications
CHAPTER 23, 25, 27, 29, and 31
ELECTRICAL SPECIFICATIONS
Addition of characteristics curves
CHAPTER 24, 26, 28, 30, and 32
CHARACTERISTICS CURVES
Addition of package drawings
CHAPTER 33 PACKAGE DRAWINGS
Addition of recommended soldering conditions
CHAPTER 34 RECOMMENDED
SOLDERING CONDITIONS
Third
edition
Overall revision of description on development tools
Deletion of embedded software
APPENDIX A DEVELOPMENT TOOLS
Change of Related Documents
INTRODUCTION
Deletion of SMB from block diagram in 1.8
CHAPTER 1 GENERAL (
PD789167
AND 789177 SUBSERIES)
Deletion of P60 to P67 from Table 6-3 Port Mode Register and
Output Latch Settings for Using Alternate Functions
CHAPTER 6 PORT FUNCTIONS
Modification of Figures 8-6 Timing of Timer Interrupt Operation and 8-
8 Timer Output Timing
CHAPTER 8 16-BIT TIMER 90
Change of description of Cautions in 9.5 Notes on Using 8-Bit
Timer/Event Counters 80 to 82
CHAPTER 9 8-BIT TIMER/EVENT
COUNTERS 80 TO 82
Modification of Notes in Figure 12-2 Format of A/D Converter Mode
Register 0
CHAPTER 12 8-BIT A/D CONVERTER
(
PD789167 AND 789167Y
SUBSERIES)
Modification of Notes in Figure 13-2 Format of A/D Converter Mode
Register 0
CHAPTER 13 10-BIT A/D
CONVERTER (
PD789177 AND
789177Y SUBSERIES)
Fourth
edition
Modification of Figure 14-1 Block Diagram of Serial Interface 20
Modification of description of Cautions in Figure 14-6 Format of Baud Rate
Generator Control Register 20
Addition of 14.3 (4) (c) Generation of serial clock from system clock
input to 3-wire serial I/O mode
CHAPTER 14 SERIAL INTERFACE 20