
708
SAM G51 [DATASHEET]
11209C–ATARM–20-Dec-13
Figure 30-29. SPI Transfer Format (CPHA = 0, 8 bits per transfer)
30.7.7.4
Receiver and Transmitter Control
30.7.7.5
Character Transmission
The characters are sent by writing in the Transmit Holding register (US_THR). An additional condition for transmitting a
character can be added when the USART is configured in SPI master mode. In the USART_MR, the value configured on
INACK field can prevent any character transmission (even if US_THR has been written) while the receiver side is not
ready (character not read). When WRDBT equals 0, the character is transmitted whatever the receiver status. If WRDBT
is set to 1, the transmitter waits for the Receive Holding register (US_RHR) to be read before transmitting the character
(RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side.
The transmitter reports two status bits in US_CSR: TXRDY (Transmitter Ready), which indicates that US_THR is empty
and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current
character processing is completed, the last character written in US_THR is transferred into the Shift register of the
transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY
is low has no effect and the written character is lost.
If the USART is in SPI slave mode and if a character must be sent while the US_THR is empty, the UNRE (Underrun
Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing a
one to the RSTSTA (Reset Status) bit in US_CR.
In SPI master mode, the slave select line (NSS) is asserted at low level 1 Tbit (Time bit) before the transmission of the
MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always
released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to
address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can
be forced at low level by writing a one to the RTSEN bit in the US_CR. The slave select line (NSS) can be released at
high level only by writing a one to the RTSDIS bit in the US_CR (for example, when all data have been transferred to the
slave device).
In SPI slave mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character
transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit
before the first serial clock cycle corresponding to the MSB bit.
SCK
(CPOL = 0)
SCK
(CPOL = 1)
12
3
45
7
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
SCK cycle (for reference)
8
MSB
LSB
6
5
4
3
1
2
6