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參數(shù)資料
| 型號： | UPD78F0361GK(S)-UET-A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 12 X 12 MM, LEAD FREE, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 24/32頁 |
| 文件大?。?/td> | 3542K |
| 代理商： | UPD78F0361GK(S)-UET-A |
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CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U17734EJ1V0UD
30
(d) RxD0, RxD6
These are the serial data input pins of the asynchronous serial interface.
(e) TxD0, TxD6
These are the serial data output pins of the asynchronous serial interface.
(f)
TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(g) TO50, TOH0, and TOH1
These are timer output pins.
(h) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
2.2.3 P20 to P24 (port 2)
P20 to P24 function as a 5-bit I/O port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P24 function as a 5-bit I/O port. P20 to P24 can be set to input or output port in 1-bit units using port
mode register 2 (PM2).
(2) Control mode
P20 to P24 function as A/D converter analog input pins (ANI0 to ANI4). When using these pins as analog input
pins, see (5) ANI0/P20 to ANI4/P24 in 12.6 Cautions for A/D Converter.
Caution
P20/ANI0 to P24/ANI4 are set in the analog input mode after release of reset.
2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and
timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output port in 1-bit units using port
mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3
(PU3).
(2) Control mode
P30 to P33 function as external interrupt request input and timer I/O.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
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