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User's Manual U11919EJ3V0UM00
17
LIST OF FIGURES (1/3)
Figure No.
Title
Page
2-1
List of Pin Input/Output Circuits................................................................................................................. 40
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
Memory Map (
μ
PD789022)....................................................................................................................... 41
Memory Map (
μ
PD789024)....................................................................................................................... 42
Memory Map (
μ
PD789025)....................................................................................................................... 43
Memory Map (
μ
PD789026)....................................................................................................................... 44
Memory Map (
μ
PD78F9026A) .................................................................................................................. 45
Data Memory Addressing (
μ
PD789022) ................................................................................................... 48
Data Memory Addressing (
μ
PD789024) ................................................................................................... 49
Data Memory Addressing (
μ
PD789025) ................................................................................................... 50
Data Memory Addressing (
μ
PD789026) ................................................................................................... 51
Data Memory Addressing (
μ
PD78F9026A)............................................................................................... 52
Program Counter Configuration ................................................................................................................ 53
Program Status Word Configuration ......................................................................................................... 53
Stack Pointer Configuration ...................................................................................................................... 55
Data to be Saved to Stack Memory .......................................................................................................... 55
Data to be Restored from Stack Memory.................................................................................................. 55
General-Purpose Register Configuration.................................................................................................. 56
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
Port Types................................................................................................................................................. 69
Block Diagram of P00 to P07.................................................................................................................... 71
Block Diagram of P10 to P17.................................................................................................................... 72
Block Diagram of P20 ............................................................................................................................... 73
Block Diagram of P21 ............................................................................................................................... 74
Block Diagram of P22 ............................................................................................................................... 75
Block Diagram of P30 to P32.................................................................................................................... 76
Block Diagram of P40 to P47.................................................................................................................... 77
Block Diagram of P50 ............................................................................................................................... 78
Block Diagram of P51 ............................................................................................................................... 79
Block Diagram of P52 and P53................................................................................................................. 80
Port Mode Register Format....................................................................................................................... 82
Pull-Up Resistor Option Register Format.................................................................................................. 82
5-1
5-2
5-3
5-4
5-5
Block Diagram of Clock Generation Circuit............................................................................................... 85
Processor Clock Control Register Format................................................................................................. 86
External Circuit of System Clock Oscillation Circuit.................................................................................. 87
Incorrect Examples of Resonator Connection........................................................................................... 88
Switching CPU Clock ................................................................................................................................ 91