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參數(shù)資料
| 型號： | UPD784907 |
| 廠商： | NEC Corp. |
| 英文描述： | 16-BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | 16位單片機 |
| 文件頁數(shù)： | 43/98頁 |
| 文件大?。?/td> | 657K |
| 代理商： | UPD784907 |
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μ
PD784907, 784908
43
Data Sheet U11680EJ2V0DS00
8.7 A/D Converter
An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0 through ANI7) is incorporated.
The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D
conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved.
A/D conversion can be started in the following two ways:
Hardware start: Conversion is started by trigger input (INTP5).
Software start: Conversion is started by setting the bit of the A/D converter mode register (ADM).
After conversion has started, one of the following modes can be selected:
Scan mode:
Select mode: A single analog input is selected at all times to enable conversion data to be obtained continuously.
Multiple analog inputs are selected sequentially to convert multiple pins.
ADM is used to specify the above modes, as well as the termination of conversion.
When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature,
the results of conversion can be continuously transferred to memory by the macro service.
Cautions
1. For this product, apply the same voltage as the power supply voltage (AV
DD
) to the reference
voltage input pin (AV
REF1
).
2. When port 7 is used as both an output port and A/D input line, do not manipulate the output
port while A/D conversion is in progress.
Figure 8-9. Block Diagram of A/D Converter
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
INTP5
AV
REF1
AV
SS
R/2
R
R/2
8
8
8
I
T
Sample and hold circuit
Voltage comparator
Successive
approximation
register (SAR)
Connection
control
A/D current cut selection
register (IEAD)
Series resistor string
Control
circuit
A/D converter mode
register (ADM)
A/D conversion
result register (ADCR)
Internal bus
Edge
detection
circuit
Conversion
trigger
Trigger enable
INTAD
AV
DD
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