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參數(shù)資料
| 型號(hào)： | UPD75P108BCW |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 23/46頁(yè) |
| 文件大小： | 381K |
| 代理商： | UPD75P108BCW |
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23
μ
PD75P108B
AC CHARACTERISTICS (Ta = –40 to +85
°
C, V
DD
= 2.7 to 6.0 V)
*
The cycle time of the CPU
clock (
Φ
) is determined by
the oscillator frequency of
the connected resonator
and the processor clock
control register (PCC). The
graph on the right shows
cycle time t
CY
characteris-
tics against supply voltage
V
DD
when system clock is
operated.
t
C
μ
s
40
Operation
Guaranteed
Range
t
CY
VS.
V
DD
V
DD
[V]
32
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0.5
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DD
= 4.5 to 6.0 V
0.95
32
μ
s
3.8
32
μ
s
V
DD
= 4.5 to 6.0 V
0
1
MHz
0
275
kHz
V
DD
= 4.5 to 6.0 V
0.48
μ
s
1.8
μ
s
Input
0.8
μ
s
Output
0.95
μ
s
Input
3.2
μ
s
Output
3.8
μ
s
Input
0.4
μ
s
Output
t
KCY
/2–50
ns
Input
1.6
μ
s
Output
t
KCY
/2–150
ns
100
ns
400
ns
V
DD
= 4.5 to 6.0 V
300
ns
1000
ns
5
μ
s
5
μ
s
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
t
CY
f
TI
t
TIH
,
t
TIL
t
KCY
t
KH
,
t
KL
t
SIK
t
KSI
t
KSO
t
INTH
,
t
INTL
t
RSL
PARAMETER
CPU clock cycle time
*
(minimum instruction
execution time = 1 ma-
chine cycle)
TI0, TI1 input frequency
TI0, TI1 input high/low-
level width
SCK cycle time
SCK high/low-level width
SI setup time (to SCK
↑
)
SI hold time (from SCK
↑
)
SO output delay time
from SCK
↓
INT0 to INT4 high/low-
level width
RESET low level width
#
#
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