- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄384045 > UPD72874GC-YEB (NEC Corp.) IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD72874GC-YEB |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER |
| 中文描述： | IEEE1394連接的OHCI 1.1標(biāo)準(zhǔn)3PORT物理層鏈路1 -芯片的主機(jī)控制器 |
| 文件頁(yè)數(shù)： | 8/40頁(yè) |
| 文件大?。?/td> | 297K |
| 代理商： | UPD72874GC-YEB |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)
Preliminary Data Sheet S15306EJ2V0DS
8
μ
PD72874
1. PIN FUNCTIONS
1.1 PCI/Cardbus Interface Signals: (52 pins)
(1/2)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
Block *
PAR
I/O
44
PCI/Cardbus
5/3.3
Parity
is even parity across AD0 to AD31 and CBE0
to CBE3. It is an input when AD0 to AD31 is an
input; it is an output when AD0 to AD31 is an output.
Link
AD0 to AD31
I/O
9, 10, 12, 13,
15 to18, 23, 24,
26 to 29, 32, 33,
47 to 50, 52, 53,
55, 56, 58, 59, 62,
63, 65 to 68
PCI/Cardbus
5/3.3
PCI Multiplexed Address and Data
Link
CBE0 to
CBE3
I/O
21, 34, 45, 57
-
5/3.3
Command/Byte Enables
are multiplexed bus
commands & byte enables.
Link
FRAME
I/O
35
PCI/Cardbus
5/3.3
Frame
is asserted by the initiator to indicate the
cycle beginning and is kept asserted during the
burst cycle. If Cardbus mode (CARD_ON = 1), this
pin should be pulled up to V
DD
.
Link
TRDY
I/O
37
PCI/Cardbus
5/3.3
Target Ready
indicates that the current data phase
of the transaction is ready to be completed.
Link
IRDY
I/O
36
PCI/Cardbus
5/3.3
Initiator Ready
indicates that the current bus
master is ready to complete the current data phase.
During a write, its assertion indicates that the
initiator is driving valid data onto the data bus.
During a read, its assertion indicates that the
initiator is ready to accept data from the currently-
addressed target.
Link
REQ
O
8
PCI/Cardbus
5/3.3
Bus_master Request
indicates to the bus arbiter
that this device wants to become a bus master.
Link
GNT
I
7
-
5/3.3
Bus_master Grant
indicates to this device that
access to the bus has been granted.
Link
IDSEL
I
22
-
5/3.3
Initialization Device Select
is used as chip select
for configuration read/write transaction during the
phase of device initialization. If Cardbus mode
(CARD_ON = 1), this pin should be pulled up to V
DD
.
Link
DEVSEL
I/O
39
PCI/Cardbus
5/3.3
Device Select
when actively driven, indicates that
the driving device has decoded its address as the
target of the current access.
Link
STOP
I/O
40
PCI/Cardbus
5/3.3
PCI Stop
when actively driven, indicates that the
target is requesting the current bus master to stop
the transaction.
Link
PME
O
3
PCI/Cardbus
5/3.3
PME Output
for power management event.
Link
Remark
*: If the Link pin is pulled up, it should be connected to L_V
DD
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD7281 | IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER |
| UPD753036 | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| UPD753304 | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| UPD753304P | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
| UPD753304W | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD74HC04C | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD750068GT-396 | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD7507C189 | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD7508CU265 | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD75208 | 制造商:Panasonic Industrial Company 功能描述:IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。