參數(shù)資料
型號: UPD72852GB-8EU
廠商: NEC Corp.
英文描述: MOS INTEGRATED CIRCUIT
中文描述: 馬鞍山集成電路
文件頁數(shù): 8/48頁
文件大?。?/td> 249K
代理商: UPD72852GB-8EU
Data Sheet S14920EJ3V0DS
8
μ
PD72852
1.3 Control Pins
Name
Pin No.
I/O
Function
PC0
26
I
PC1
27
I
PC2
28
I
Power class set input
This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H.
IEEE1394a-2000 chapter [4.3.4.1]
CMC
30
I
Configuration manager capable setting
This pin status will be loaded to Contender bit which allocated to PHY register 4H.
0: Non contender
1: Contender
RESETB
55
I
Power-on reset input
Connect to GND through a 0.1
μ
F capacitor.
0: Reset
1: Normal
SPD
61
I
Speed select
0: MAX. S200
1: MAX. S400
1.4 IC
Name
Pin No.
I/O
Function
IC(AL)
29, 51
-
Internally Connected (Low Clamped)
Connect to GND.
IC(DL)
3
-
Internally Connected (Low Clamped)
Connect to GND.
1.5 Power Supply Pins
Name
Pin No.
I/O
Function
AV
DD
25, 31, 40, 47, 54
-
Analog power
AGND
24, 33, 35, 42, 49, 52, 53
-
Analog GND
DV
DD
4, 10, 20, 56, 60
-
Digital V
DD
DGND
1, 7, 13, 16, 21, 57, 64
-
Digital GND
1.6 Other Pins
Name
Pin No.
I/O
Function
TpBias0
41
O
Port 0 twisted pair output
TpBias1
48
O
Port 1 twisted pair output
RI1
34
-
Resistor connection pin1 for reference current generator
Connect to GND through a 9.1 k
resistor.
XI
23
-
Crystal oscillator connection XI
XO
22
-
Crystal oscillator connection XO
TEST
62
-
Test pin
Internally connected (Low clamped).
Connect to GND.
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