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參數(shù)資料
| 型號： | UPD72852 |
| 廠商： | NEC Corp. |
| 英文描述： | MOS INTEGRATED CIRCUIT |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 29/48頁 |
| 文件大?。?/td> | 249K |
| 代理商： | UPD72852 |
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Data Sheet S14920EJ3V0DS
29
μ
PD72852
4.6 Transmit
The
μ
PD72852 arbitrates the serial bus using Link’s LREQ.
When the
μ
PD72852 acquires the bus, a Grant period of 1 SCLK is executed to CTL0, CTL1. After that, an Idle
period of 1 SCLK cycle is executed.
Link controls the interface executing Idle, Hold of Transmit to CTL0, CTL1 after 1 SCLK cycle when Grant from
PHY is detected.
Before asserting Hold and Transmit, assert 1 Idle cycle. Do not execute Idle for 2 or more cycles.
If the packet transmit is not ready, the Hold period can be extended up to MAX_HOLD.
The
μ
PD72852 outputs DATA_PREFIX to the serial bus while Hold is being asserted to CTL.
When the packet transmit is ready, Link outputs the first bit of the packet and Transmit is asserted to CTL at the
same time.
After transmitting the last bit of the packet, Link outputs for Idle or Hold to CTL for 1 cycle. After that, it outputs
Idle for 1 cycle.
When PHY/Link releases the bus, output Low to CTL and D0-D7 within 1 cycle.
Figure 4-5. Transmit Timing
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
ZZ
ZZ
ZZ
00
01
01
10
10
10
10
00
00
ZZ
ZZ
ZZ
ZZ
00
00
00
D0
D1
D2
D
n
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
00
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
ZZ
10
10
01
00
ZZ
ZZ
ZZ
ZZ
01
10
10
D
n-1
D
n
SP
00
ZZ
ZZ
ZZ
ZZ
00
D0
D1
ZZ
ZZ
01
00
(a) Single Packet
PHY CTL0,CTL1
PHY D0-D7
Link CTL0,CTL1
Link D0-D7
(b) Concatenated Packet
PHY CTL0,CTL1
PHY D0-D7
Link CTL0,CTL1
Link D0-D7
ZZ
ZZ
00
00
Note
In case of packet transmission after Grant, before actual transmission, Hold does not need to be asserted.
Link can transmit continuous packets without releasing the bus.
Hold is asserted to CTL. This function is used when the Link transmits continuous packets after acknowledge and
isochronous packets. Link outputs the transfer rate signal of the following packet to D0-D7 and asserts Hold
simultaneously.
After Hold is detected by MIN_PACKET_SEPARATION, the
μ
PD72852 outputs Grant to CTL.
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