參數(shù)資料
型號(hào)： UPD72852
廠商： NEC Corp.
英文描述： MOS INTEGRATED CIRCUIT
中文描述： 馬鞍山集成電路
文件頁(yè)數(shù)： 28/48頁(yè)
文件大?。?/td> 249K
代理商： UPD72852
Data Sheet S14920EJ3V0DS
28
μ
PD72852
4.5 Transmit Status
Pin D0, D1 of the
μ
PD72852 transmits status information to the Link. Status is asserted to CTL while transmitting
Status. The status transmission is interrupted if the serial bus receives a packet which contains states other than
status to CTL. Between two status transmissions, assert Idle to CTL for at least one SCLK cycle.
The
μ
PD72852 transmits status in 16 bits as follows:
In response to the register request
After deciding the new Physical_ID for the Self_ID period resetting the bus (after a Self_ID packet is transmitted)
The event indication is the only 4-bit transmission of the
μ
PD72852.
Figure 4-4. Status Timing
00
01
01
00
00
00
S0,S1
S2,S3
00
00
PHY CTL0,CTL1
PHY D0-D7
01
S14,
S15
Table 4-13. Status Data Format
Bit(s)
Name
Description
0
ARB_RESET_GAP
Arbitration Reset gap detect
1
SUBACTION_GAP
Subaction gap detect
2
BUS_RESET_START
Bus reset detect
3
Phy_interrupt
Either of the following states is detected:
The topology of the bus is a loop
Voltage drop on the power cable
Arbitration state machine timeout
Port Event
4-7
Address
PHY register address
8-15
Data
Register data
The bits already transmitted are set to 0.
Example
If the status transmission is interrupted after S0, S1 bit was transmitted, then in the next status transfer,
S0, S1 becomes 0.
Therefore one of the following situations will occur when the
μ
PD72852 re-transmits status after an
interruption of the status transmission:
At least one bit of S0-S3 is 1
The PHY register data contains the interrupt status information
The status transmission always begins with S0, S1.
If the Link executes read request, and Subaction gap and arbitration reset gap are detected, priority is given to the
transmission of gap status, postponing the response to the register read request.
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