參數(shù)資料
型號(hào)： UPD7281
廠商： NEC Corp.
英文描述： IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER
中文描述： IEEE1394連接的OHCI 1.1標(biāo)準(zhǔn)3PORT物理層鏈路1 -芯片的主機(jī)控制器
文件頁(yè)數(shù)： 6/40頁(yè)
文件大小： 297K
代理商： UPD7281
Preliminary Data Sheet S15306EJ2V0DS
6
μ
PD72874
CONTENTS
1. PIN FUNCTIONS..................................................................................................................................... 8
1.1 PCI/Cardbus Interface Signals: (52 pins)...................................................................................... 8
1.2 PHY Signals: (20 pins) .................................................................................................................. 10
1.3 PHY Control Signals: (4 pins)....................................................................................................... 10
1.4 PCI/Cardbus Select Signal: (1 pin)............................................................................................... 10
1.5 Serial ROM Interface Signals: (3 pins)......................................................................................... 11
1.6 D3cold Wake Up Function Signals: (2 pins)............................................................................... 11
1.7 IC: (7 pins)...................................................................................................................................... 11
1.8 V
DD
................................................................................................................................................... 12
1.9 GND................................................................................................................................................. 12
2. PHY REGISTERS................................................................................................................................... 13
2.1 Complete Structure for PHY Registers........................................................................................ 13
2.2 Port Status Page (Page 000)......................................................................................................... 16
2.3 Vendor ID Page (Page 001)........................................................................................................... 17
2.4 Vendor Dependent Page (Page 111 : Port_select 0001) ............................................................ 17
3. CONFIGURATION REGISTERS .......................................................................................................... 18
3.1 PCI Bus Mode Configuration Register (CARD_ON = Low)........................................................ 18
3.1.1 Offset_00 Vendor ID Register ...........................................................................................................19
3.1.2 Offset_02 Device ID Register............................................................................................................19
3.1.3 Offset_04 Command Register...........................................................................................................19
3.1.4 Offset_06 Status Register.................................................................................................................20
3.1.5 Offset_08 Revision ID Register.........................................................................................................21
3.1.6 Offset_09 Class Code Register.........................................................................................................21
3.1.7 Offset_0C Cache Line Size Register.................................................................................................21
3.1.8 Offset_0D Latency Timer Register....................................................................................................21
3.1.9 Offset_0E Header Type Register ......................................................................................................21
3.1.10 Offset_0F BIST Register ..................................................................................................................21
3.1.11 Offset_10 Base Address 0 Register................................................................................................22
3.1.12 Offset_2C Subsystem Vendor ID Register......................................................................................22
3.1.13 Offset_2E Subsystem ID Register...................................................................................................22
3.1.14 Offset_34 Cap_Ptr Register ............................................................................................................22
3.1.15 Offset_3C Interrupt Line Register....................................................................................................22
3.1.16 Offset_3D Interrupt Pin Register .....................................................................................................23
3.1.17 Offset_3E Min_Gnt Register ...........................................................................................................23
3.1.18 Offset_3F Max_Lat Register ...........................................................................................................23
3.1.19 Offset_40 PCI_OHCI_Control Register...........................................................................................23
3.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register..................................................................................23
3.1.21 Offset_62 Power Management Capabilities Register......................................................................24
3.1.22 Offset_64 Power Management Control/Status Register..................................................................25
3.2 CardBus Mode Configuration Register (CARD_ON = High)...................................................... 26
3.2.1 Offset_14/18 Base Address 1/2 Register (Cardbus Status Registers)..............................................27
3.2.2 Offset_28 Cardbus CIS Pointer.........................................................................................................28
3.2.3 Offset_80 CIS Area ...........................................................................................................................28
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