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參數(shù)資料
| 型號(hào)： | UPD7281 |
| 廠商： | NEC Corp. |
| 英文描述： | IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER |
| 中文描述： | IEEE1394連接的OHCI 1.1標(biāo)準(zhǔn)3PORT物理層鏈路1 -芯片的主機(jī)控制器 |
| 文件頁數(shù)： | 11/40頁 |
| 文件大小： | 297K |
| 代理商： | UPD7281 |
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Preliminary Data Sheet S15306EJ2V0DS
11
μ
PD72874
1.5 Serial ROM Interface Signals: (3 pins)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
Block *
GROM_SDA
I/O
116
6 mA
3.3
Serial EEPROM Data Input / Output
Link
GROM_SCL
O
117
6 mA
3.3
Serial EEPROM Clock Output
Link
GROM_EN
I
118
-
3.3
Serial EEPROM Enable
1: GUID Load enable
0: GUID Load disable
Link
Remark
*: If the Link pin is pulled up, it should be connected to L_V
DD
.
1.6 D3cold Wake Up Function Signals: (2 pins)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
Block *
D3CSUP
I
114
-
5/3.3
D3cold Support
1: D3cold wake up enable
0: D3cold wake up disable
Link
RSMRST
I
74
-
5/3.3
Resume Reset
D3cold support (114 pin) = ‘1’
As this mode supports D3cold wake up,
RSMRST must connect system RSMRST
signal.
D3cold support (114 pin) = ‘0’
As this mode is the
μ
PD72872 compatible,
RSMRST clamp to ‘1’.
Link
Remark
*: If the Link pin is pulled up, it should be connected to L_V
DD
.
1.7 IC: (7 pins)
Name
I/O
Pin No.
I
OL
Volts(V)
Function
Block *
IC(H)
I
75
-
-
Internally Connected
(High clamped)
Link
IC(L)
I
76 to 78, 80, 115
-
-
Internally Connected
(Low clamped)
-
IC(N)
-
85
-
-
Internally Connected
(Open)
-
Remark
*: If the Link pin is pulled up, it should be connected to L_V
DD
.
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