PD720113 APLL : Generates all clocks of Hub. ALL_TT : Translates the high-sp" />
參數(shù)資料
型號: UPD720113GK-9EU-A
廠商: Renesas Electronics America
文件頁數(shù): 30/34頁
文件大?。?/td> 0K
描述: IC HUB CTLR USB2.0 7-PORTS QFP
標(biāo)準(zhǔn)包裝: 50
控制器類型: USB 2.0 集線器控制器
接口: USB 2.0
電源電壓: 2.5 V,3.3 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 80-TQFP
供應(yīng)商設(shè)備封裝: 80-TQFP
包裝: 托盤
Data Sheet S16618EJ3V0DS
3
PD720113
APLL
: Generates all clocks of Hub.
ALL_TT
: Translates the high-speed transactions (split transactions) for full/low-speed device
to full/low-speed transactions.
ALL_TT buffers the data transfer from either
upstream or downstream direction. For OUT transaction, ALL_TT buffers data from
upstream port and sends it out to the downstream facing ports after speed
conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers
data from downstream ports and sends it out to the upstream facing ports after
speed conversion from full/low-speed to high-speed.
CDR
: Data & clock recovery circuit
DPC
: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and
Resume
DP(n)_PHY
: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and
low-speed (1.5 Mbps) transaction
EP0
: Endpoint 0 controller
EP1
: Endpoint 1 controller
F_TIM (Frame Timer)
: Manages hub’s synchronization by using micro-SOF which is received at upstream
port, and generates SOF packet when full/low-speed device is attached to
downstream facing port.
FS_REP
: Full/low-speed repeater is enabled when the
PD720113 are worked at full-speed
mode
OSB
: Oscillator Block
ROM I/F
: Interface block for external Serial ROM which contains user-defined descriptors
SERDES
: Serializer and Deserializer
SIE_2H
: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer.
UP_PHY
: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)
transaction
UPC
: Upstream Port Controller handles Suspend and Resume
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