PD720113 2.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Sy" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� UPD720113GK-9EU-A
寤犲晢锛� Renesas Electronics America
鏂囦欢闋佹暩(sh霉)锛� 2/34闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC HUB CTLR USB2.0 7-PORTS QFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 50
鎺у埗鍣ㄩ鍨嬶細 USB 2.0 闆嗙窔鍣ㄦ帶鍒跺櫒
鎺ュ彛锛� USB 2.0
闆绘簮闆诲锛� 2.5 V锛�3.3 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 80-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 80-TQFP
鍖呰锛� 鎵樼洡
Data Sheet S16618EJ3V0DS
8
PD720113
2.2
Terminology
Terms Used in Absolute Maximum Ratings
Parameter
Symbol
Meaning
Power supply voltage
VDD33
VDD25
AVDD
Indicates voltage range within which damage or reduced reliability will not
result when power is applied to a VDD pin.
Input voltage
VI
Indicates voltage range within which damage or reduced reliability will not
result when power is applied to an input pin.
Output voltage
VO
Indicates voltage range within which damage or reduced reliability will not
result when power is applied to an output pin.
Output current
IO
Indicates absolute tolerance values for DC current to prevent damage or
reduced reliability when current flows out of or into an output pin.
Operating temperature
TA
Indicates the ambient temperature range for normal logic operations.
Storage temperature
Tstg
Indicates the element temperature range within which damage or reduced
reliability will not result while no voltage or current are applied to the device.
Terms Used in Recommended Operating Range
Parameter
Symbol
Meaning
Power supply voltage
VDD33
VDD25
AVDD
Indicates the voltage range for normal logic operations to occur when VSS = 0
V.
High-level input voltage
VIH
Indicates the voltage, applied to the input pins of the device, which indicates
the high level state for normal operation of the input buffer.
* If a voltage that is equal to or greater than the 鈥淢IN.鈥� value is applied, the
input voltage is guaranteed as high level voltage.
Low-level input voltage
VIL
Indicates the voltage, applied to the input pins of the device, which indicates
the low level state for normal operation of the input buffer.
* If a voltage that is equal to or less than the 鈥淢AX.鈥� value is applied, the
input voltage is guaranteed as low level voltage.
Hysteresis voltage
VH
Indicates the differential between the positive trigger voltage and the negative
trigger voltage.
Input rise time
tri
Indicates allowable input signal transition time from 0.1
脳 VDD to 0.9 脳 VDD.
Input fall time
tfi
Indicates allowable input signal transition time from 0.9
脳 VDD to 0.1 脳 VDD.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
UPD78F0394GC-8EA-A MCU 8BIT 48KB FLASH
UPD78F1146AF1-AN1-A MCU 16BIT 78K0R/KX3 64-FBGA
UPD78F1156AGC-GAD-AX MCU 16BIT 78K0R/KX3 80-LQFP
UPD78F1168AGF-GAS-AX MCU 16BIT 78K0R/KX3 100-LQFP
UPD78F1178AGF-GAT-AX MCU 16BIT 78K0R/KX3 128-LQFP
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
UPD720114GA-9EU-A 鍒堕€犲晢:Renesas Electronics Corporation 鍔熻兘鎻忚堪:I/O Controller USB Controller 48-Pin TQFP 鍒堕€犲晢:NEC Electronics Corporation 鍔熻兘鎻忚堪:HUB CONTROLLER 4 PORT USB TQFP48
UPD720114GA-YEU-A 鍔熻兘鎻忚堪:HOST CTLR USB 2.0 48-TQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 鎺у埗鍣� 绯诲垪:ECOUSB™ 妯�(bi膩o)婧�(zh菙n)鍖呰:2,450 绯诲垪:- 鎺у埗鍣ㄩ鍨�:SPI 绺界窔鑷� I²C 绺界窔姗嬫帴 鎺ュ彛:I²C锛屼覆琛�锛孲PI 闆绘簮闆诲:2.4 V ~ 3.6 V 闆绘祦 - 闆绘簮:11mA 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-HVQFN锛�4x4锛� 鍖呰:鎵樼洡 閰嶇敤:568-3511-ND - DEMO BOARD SPI TO I2C 鍏跺畠鍚嶇ū:935286452157SC18IS600IBSSC18IS600IBS-ND
UPD720114GA-YEU-ATR 鍒堕€犲晢:Renesas Electronics Corporation 鍔熻兘鎻忚堪:I/O CNTRLR USB CNTRLR 48TQFP - Trays
UPD720114K9-4E4-A 鍒堕€犲晢:Renesas Electronics Corporation 鍔熻兘鎻忚堪:USB2.0 HUB CTRL, 4-PORTS, 40-PIN PLASTIC QFN (6MMX6MM) - Trays
UPD720114K9-4E4-SSA-A 鍒堕€犲晢:Renesas Electronics Corporation 鍔熻兘鎻忚堪:
鐧�(f膩)甯冪穵鎬ラ噰璩�锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣闇€姹�

(鑻ュ彧閲囪臣涓€姊濆瀷铏�(h脿o)锛屽～瀵竴琛屽嵆鍙�)

鐧�(f膩)甯冩垚鍔燂紒鎮ㄥ彲浠ョ辜绾�(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

鐧�(f膩)甯冩垚鍔燂紒鎮ㄥ彲浠ョ辜绾�(x霉)鐧�(f膩)甯冮噰璩�銆備篃鍙互閫�(j矛n)鍏ユ垜鐨勫悗鑷�(t谩i)锛屾煡鐪嬪牨(b脿o)鍍�(ji脿)

*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣

鎴戠殑鑱�(li谩n)绯绘柟寮�

*
*
*
    • 閹达拷
    • 闁插洩鍠�
    • 閹兼粎鍌�
    • 娴兼艾鎲�