參數(shù)資料
型號(hào)： UPD720101GJ-UEN-A
廠商： Renesas Electronics America
文件頁(yè)數(shù)： 23/38頁(yè)
文件大?。?/td> 0K
描述： HOST CTLR USB 2.0 144-LQFP
標(biāo)準(zhǔn)包裝： 100
控制器類型： USB 外設(shè)控制器
接口： PCI
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP
包裝： 托盤
其它名稱： 972-1001
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS INTEGRATED CIRCUIT
PD720101
USB 2.0 HOST CONTROLLER
Document No.
S16265EJ5V0DS00 (5th edition)
Date Published March 2005 NS CP (N)
Printed in Japan
DATA SHEET
The mark
shows major revised points.
2002
The
PD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for
high-speed signaling and works up to 480 Mbps. The
PD720101 is integrated 3 host controller cores with PCI
interface and USB 2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
PD720101 User’s Manual: S16336E
FEATURES
Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)
Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0
PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI
host controller core for high-speed signaling.
Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
Configurable number of downstream facing ports (2 to 5)
32-bit 33 MHz host interface compliant to PCI Specification release 2.2
Supports PCI Mobile Design Guide Revision 1.1
Supports PCI-Bus Power Management Interface Specification release 1.1
PCI bus bus-master access
System clock is generated by 30 MHz X’tal or 48 MHz clock input.
System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see
PD720101
User’s Manual.
Operational registers direct-mapped to PCI memory space
Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number
Package
Remark
PD720101GJ-UEN
144-pin plastic LQFP (Fine pitch) (20
× 20)
PD720101GJ-UEN-A
144-pin plastic LQFP (Fine pitch) (20
× 20)
Lead-free product
PD720101F1-EA8
144-pin plastic FBGA (12
× 12)
PD720101F1-EA8-A
144-pin plastic FBGA (12
× 12)
Lead-free product
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD720101GJ-UEN-A/UJ 制造商:NEC Electronics Corporation 功能描述:HOST CONTROLLER USB 2.0 LQFP144
UPD720102F1-CA7-A 功能描述:IC HOST CTLR USB2.0 3-PORT BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
UPD720102GC-YEB-A 功能描述:IC HOST CTLR USB2.0 3-PORTS QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
UPD720112GK-9EU 制造商: 功能描述: 制造商:NEC Electronics Corporation 功能描述: 制造商:undefined 功能描述:
UPD720113GK-9EU-A 功能描述:IC HUB CTLR USB2.0 7-PORTS QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A
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